Commit 4a526957 authored by Phil Edworthy's avatar Phil Edworthy Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC 



Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 049bddcb

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+8 −5
Original line number Diff line number Diff line
@@ -4,14 +4,15 @@ 
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.

  Standby Mode share the same register block. On RZ/V2M, the functionality is

  similar, but does not have Clock Monitor Registers.



  They provide the following functionalities:

    - The CPG block generates various core clocks,
@@ -26,6 +27,7 @@ properties: 
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

    maxItems: 1
@@ -43,9 +45,10 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g*-cpg.h>

        <dt-bindings/clock/r9a0*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or

        <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -59,7 +62,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 1



required: