Loading arch/arm/mach-imx/anatop.c +4 −2 Original line number Diff line number Diff line Loading @@ -94,7 +94,7 @@ void imx_anatop_post_resume(void) void __init imx_init_revision_from_anatop(void) { struct device_node *np; struct device_node *np, *src_np; void __iomem *anatop_base; unsigned int revision; u32 digprog; Loading Loading @@ -135,9 +135,10 @@ void __init imx_init_revision_from_anatop(void) void __iomem *src_base; u32 sbmr2; np = of_find_compatible_node(NULL, NULL, src_np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-src"); src_base = of_iomap(np, 0); of_node_put(src_np); WARN_ON(!src_base); sbmr2 = readl_relaxed(src_base + SRC_SBMR2); iounmap(src_base); Loading @@ -149,6 +150,7 @@ void __init imx_init_revision_from_anatop(void) } } } of_node_put(np); mxc_set_cpu_type(digprog >> 16 & 0xff); imx_set_soc_revision(revision); Loading arch/arm/mach-imx/gpc.c +1 −0 Original line number Diff line number Diff line Loading @@ -282,4 +282,5 @@ void __init imx_gpc_check_dt(void) /* map GPC, so that at least CPUidle and WARs keep working */ gpc_base = of_iomap(np, 0); } of_node_put(np); } arch/arm/mach-imx/platsmp.c +1 −0 Original line number Diff line number Diff line Loading @@ -109,6 +109,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg"); dcfg_base = of_iomap(np, 0); of_node_put(np); BUG_ON(!dcfg_base); paddr = __pa_symbol(secondary_startup); Loading arch/arm/mach-imx/pm-imx6.c +2 −0 Original line number Diff line number Diff line Loading @@ -655,6 +655,8 @@ void __init imx6_pm_ccm_init(const char *ccm_compat) if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) imx6_pm_stby_poweroff_probe(); of_node_put(np); } void __init imx6q_pm_init(void) Loading arch/arm/mach-imx/pm-imx7ulp.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ void __init imx7ulp_pm_init(void) np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); smc1_base = of_iomap(np, 0); of_node_put(np); WARN_ON(!smc1_base); imx7ulp_set_lpm(ULP_PM_RUN); Loading Loading
arch/arm/mach-imx/anatop.c +4 −2 Original line number Diff line number Diff line Loading @@ -94,7 +94,7 @@ void imx_anatop_post_resume(void) void __init imx_init_revision_from_anatop(void) { struct device_node *np; struct device_node *np, *src_np; void __iomem *anatop_base; unsigned int revision; u32 digprog; Loading Loading @@ -135,9 +135,10 @@ void __init imx_init_revision_from_anatop(void) void __iomem *src_base; u32 sbmr2; np = of_find_compatible_node(NULL, NULL, src_np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-src"); src_base = of_iomap(np, 0); of_node_put(src_np); WARN_ON(!src_base); sbmr2 = readl_relaxed(src_base + SRC_SBMR2); iounmap(src_base); Loading @@ -149,6 +150,7 @@ void __init imx_init_revision_from_anatop(void) } } } of_node_put(np); mxc_set_cpu_type(digprog >> 16 & 0xff); imx_set_soc_revision(revision); Loading
arch/arm/mach-imx/gpc.c +1 −0 Original line number Diff line number Diff line Loading @@ -282,4 +282,5 @@ void __init imx_gpc_check_dt(void) /* map GPC, so that at least CPUidle and WARs keep working */ gpc_base = of_iomap(np, 0); } of_node_put(np); }
arch/arm/mach-imx/platsmp.c +1 −0 Original line number Diff line number Diff line Loading @@ -109,6 +109,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg"); dcfg_base = of_iomap(np, 0); of_node_put(np); BUG_ON(!dcfg_base); paddr = __pa_symbol(secondary_startup); Loading
arch/arm/mach-imx/pm-imx6.c +2 −0 Original line number Diff line number Diff line Loading @@ -655,6 +655,8 @@ void __init imx6_pm_ccm_init(const char *ccm_compat) if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) imx6_pm_stby_poweroff_probe(); of_node_put(np); } void __init imx6q_pm_init(void) Loading
arch/arm/mach-imx/pm-imx7ulp.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ void __init imx7ulp_pm_init(void) np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); smc1_base = of_iomap(np, 0); of_node_put(np); WARN_ON(!smc1_base); imx7ulp_set_lpm(ULP_PM_RUN); Loading