Commit 4a4e31c6 authored by Ke Chen's avatar Ke Chen Committed by Wang Wensheng
Browse files

net: hns3: HNAE3 framework add support for ROH client 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5WKYW



-----------------------------------------------------------------------

HNAE3 framework supports ROH clients to register with HNAE3
devices and their associated operations.

The ROH driver works as a client at the HNAE layer. The NIC
driver needs to provide some necessary information, such as
the vector base address, and suppor the registration of the
ROH client.

This patch also supports roh device IDs in the hns3 and hclge
modules.

Signed-off-by: default avatarYufeng Mo <moyufeng@huawei.com>
Signed-off-by: default avatarKe Chen <chenke54@huawei.com>
Reviewed-by: default avatarGang Zhang <gang.zhang@huawei.com>
Reviewed-by: default avatarYefeng Yan <yanyefeng@huawei.com>
Reviewed-by: default avatarJingchao Dai <daijingchao1@huawei.com>
Reviewed-by: default avatarJian Shen <shenjian15@huawei.com>
parent ef16aa34

drivers/net/ethernet/hisilicon/hns3/hnae3.c

+9 −1
Original line number Diff line number Diff line
@@ -40,7 +40,8 @@ static DEFINE_MUTEX(hnae3_common_lock); 
static bool hnae3_client_match(enum hnae3_client_type client_type)

{

	if (client_type == HNAE3_CLIENT_KNIC ||

	    client_type == HNAE3_CLIENT_ROCE)

	    client_type == HNAE3_CLIENT_ROCE ||

	    client_type == HNAE3_CLIENT_ROH)

		return true;



	return false;
@@ -60,6 +61,9 @@ void hnae3_set_client_init_flag(struct hnae3_client *client, 
	case HNAE3_CLIENT_ROCE:

		hnae3_set_bit(ae_dev->flag, HNAE3_ROCE_CLIENT_INITED_B, inited);

		break;

	case HNAE3_CLIENT_ROH:

		hnae3_set_bit(ae_dev->flag, HNAE3_ROH_CLIENT_INITED_B, inited);

		break;

	default:

		break;

	}
@@ -80,6 +84,10 @@ static int hnae3_get_client_init_flag(struct hnae3_client *client, 
		inited = hnae3_get_bit(ae_dev->flag,

				       HNAE3_ROCE_CLIENT_INITED_B);

		break;

	case HNAE3_CLIENT_ROH:

		inited = hnae3_get_bit(ae_dev->flag,

				       HNAE3_ROH_CLIENT_INITED_B);

		break;

	default:

		break;

	}

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+12 −0
Original line number Diff line number Diff line
@@ -51,7 +51,10 @@ 
#define HNAE3_DEV_ID_50GE_RDMA			0xA224

#define HNAE3_DEV_ID_50GE_RDMA_MACSEC		0xA225

#define HNAE3_DEV_ID_100G_RDMA_MACSEC		0xA226

#define HNAE3_DEV_ID_100G_ROH			0xA227

#define HNAE3_DEV_ID_200G_RDMA			0xA228

#define HNAE3_DEV_ID_200G_ROH			0xA22C

#define HNAE3_DEV_ID_400G_ROH			0xA22D

#define HNAE3_DEV_ID_VF				0xA22E

#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF		0xA22F
@@ -63,6 +66,7 @@ 
#define HNAE3_KNIC_CLIENT_INITED_B		0x3

#define HNAE3_UNIC_CLIENT_INITED_B		0x4

#define HNAE3_ROCE_CLIENT_INITED_B		0x5

#define HNAE3_ROH_CLIENT_INITED_B		0x6



#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \

		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
@@ -197,6 +201,7 @@ enum hnae3_loop { 
enum hnae3_client_type {

	HNAE3_CLIENT_KNIC,

	HNAE3_CLIENT_ROCE,

	HNAE3_CLIENT_ROH,

};



/* mac media type */
@@ -827,6 +832,12 @@ struct hnae3_roce_private_info { 
	unsigned long state;

};



struct hnae3_roh_private_info {

	struct net_device *netdev;

	void __iomem *roh_io_base;

	int base_vector;

};



#define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)

#define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)

#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
@@ -859,6 +870,7 @@ struct hnae3_handle { 
		struct net_device *netdev; /* first member */

		struct hnae3_knic_private_info kinfo;

		struct hnae3_roce_private_info rinfo;

		struct hnae3_roh_private_info rohinfo;

	};



	u32 numa_node_mask;	/* for multi-chip support */

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+9 −0
Original line number Diff line number Diff line
@@ -94,8 +94,14 @@ static const struct pci_device_id hns3_pci_tbl[] = { 
	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_ROH),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_ROH),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_400G_ROH),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},

	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),

	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
@@ -3044,7 +3050,10 @@ bool hns3_is_phys_func(struct pci_dev *pdev) 
	case HNAE3_DEV_ID_50GE_RDMA:

	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:

	case HNAE3_DEV_ID_100G_RDMA_MACSEC:

	case HNAE3_DEV_ID_100G_ROH:

	case HNAE3_DEV_ID_200G_RDMA:

	case HNAE3_DEV_ID_200G_ROH:

	case HNAE3_DEV_ID_400G_ROH:

		return true;

	case HNAE3_DEV_ID_VF:

	case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+2 −1
Original line number Diff line number Diff line
@@ -180,7 +180,8 @@ struct hclge_pf_res_cmd { 
	__le16 tx_buf_size;

	__le16 dv_buf_size;

	__le16 ext_tqp_num;

	u8 rsv[6];

	__le16 pf_intr_vector_number_roh;

	u8 rsv[4];

};



#define HCLGE_CFG_OFFSET_S	0

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -1740,6 +1740,8 @@ static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len) 
			 hdev->num_nic_msi);

	pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n",

			 hdev->num_roce_msi);

	pos += scnprintf(buf + pos, len - pos, "num_roh_msi: %u\n",

			 hdev->num_roh_msi);

	pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n",

			 hdev->num_msi_used);

	pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n",