Unverified Commit 4a47fcdb authored by Jon Lin's avatar Jon Lin Committed by Mark Brown
Browse files

spi: rockchip: Set rx_fifo interrupt waterline base on transfer item 



The error here is to calculate the width as 8 bits. In fact, 16 bits
should be considered.

Signed-off-by: default avatarJon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210621104800.19088-4-jon.lin@rock-chips.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0f4f58b8

drivers/spi/spi-rockchip.c

+2 −2
Original line number Diff line number Diff line
@@ -540,8 +540,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs, 
	 * interrupt exactly when the fifo is full doesn't seem to work,

	 * so we need the strict inequality here

	 */

	if (xfer->len < rs->fifo_len)

		writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);

	if ((xfer->len / rs->n_bytes) < rs->fifo_len)

		writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);

	else

		writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);