Commit 4a1dcf77 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'i2c-for-5.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c fixes from Wolfram Sang:
 "Two driver bugfixes and a typo fix"

* tag 'i2c-for-5.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: cadence: Change large transfer count reset logic to be unconditional
  i2c: imx: fix typo in comment
  i2c: mlxcpld: Fix register setting for 400KHz frequency
parents 6f8e4e10 4ca8ca87

drivers/i2c/busses/i2c-cadence.c

+5 −25
Original line number Diff line number Diff line
@@ -388,9 +388,9 @@ static irqreturn_t cdns_i2c_slave_isr(void *ptr) 
 */

static irqreturn_t cdns_i2c_master_isr(void *ptr)

{

	unsigned int isr_status, avail_bytes, updatetx;

	unsigned int isr_status, avail_bytes;

	unsigned int bytes_to_send;

	bool hold_quirk;

	bool updatetx;

	struct cdns_i2c *id = ptr;

	/* Signal completion only after everything is updated */

	int done_flag = 0;
@@ -410,11 +410,7 @@ static irqreturn_t cdns_i2c_master_isr(void *ptr) 
	 * Check if transfer size register needs to be updated again for a

	 * large data receive operation.

	 */

	updatetx = 0;

	if (id->recv_count > id->curr_recv_count)

		updatetx = 1;



	hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;

	updatetx = id->recv_count > id->curr_recv_count;



	/* When receiving, handle data interrupt and completion interrupt */

	if (id->p_recv_buf &&
@@ -445,7 +441,7 @@ static irqreturn_t cdns_i2c_master_isr(void *ptr) 
				break;

			}



			if (cdns_is_holdquirk(id, hold_quirk))

			if (cdns_is_holdquirk(id, updatetx))

				break;

		}
@@ -456,7 +452,7 @@ static irqreturn_t cdns_i2c_master_isr(void *ptr) 
		 * maintain transfer size non-zero while performing a large

		 * receive operation.

		 */

		if (cdns_is_holdquirk(id, hold_quirk)) {

		if (cdns_is_holdquirk(id, updatetx)) {

			/* wait while fifo is full */

			while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=

			       (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
@@ -478,22 +474,6 @@ static irqreturn_t cdns_i2c_master_isr(void *ptr) 
						  CDNS_I2C_XFER_SIZE_OFFSET);

				id->curr_recv_count = id->recv_count;

			}

		} else if (id->recv_count && !hold_quirk &&

						!id->curr_recv_count) {



			/* Set the slave address in address register*/

			cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,

						CDNS_I2C_ADDR_OFFSET);



			if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {

				cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,

						CDNS_I2C_XFER_SIZE_OFFSET);

				id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;

			} else {

				cdns_i2c_writereg(id->recv_count,

						CDNS_I2C_XFER_SIZE_OFFSET);

				id->curr_recv_count = id->recv_count;

			}

		}



		/* Clear hold (if not repeated start) and signal completion */

drivers/i2c/busses/i2c-imx.c

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ 


/* IMX I2C registers:

 * the I2C register offset is different between SoCs,

 * to provid support for all these chips, split the

 * to provide support for all these chips, split the

 * register offset into a fixed base address and a

 * variable shift value, then the full register offset

 * will be calculated by

drivers/i2c/busses/i2c-mlxcpld.c

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ 
#define MLXCPLD_LPCI2C_NACK_IND		2



#define MLXCPLD_I2C_FREQ_1000KHZ_SET	0x04

#define MLXCPLD_I2C_FREQ_400KHZ_SET	0x0c

#define MLXCPLD_I2C_FREQ_400KHZ_SET	0x0e

#define MLXCPLD_I2C_FREQ_100KHZ_SET	0x42



enum mlxcpld_i2c_frequency {