Commit 4a0225c3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "The only core work for SPI this time around is the completion of the
  conversion to the new style method for specifying transfer delays,
  meaning we can cope with what most controllers support more directly
  using conversions in the core rather than open coding in drivers.

  Otherwise it's a good stack of cleanups and fixes plus a few new
  drivers.

  Summary:

   - Completion of the conversion to new style transfer delay
     configuration

   - Introduction and use of module_parport_driver() helper, merged here
     as there's no parport tree

   - Support for Altera SoCs on DFL buses, NXP i.MX8DL, HiSilicon
     Kunpeng, MediaTek MT8195"

* tag 'spi-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (113 commits)
  spi: Rename enable1 to activate in spi_set_cs()
  spi: Convert Freescale QSPI binding to json schema
  spi: stm32-qspi: fix debug format string
  spi: tools: make a symbolic link to the header file spi.h
  spi: fsi: add a missing of_node_put
  spi: Make error handling of gpiod_count() call cleaner
  spidev: Add Micron SPI NOR Authenta device compatible
  spi: brcm,spi-bcm-qspi: convert to the json-schema
  spi: altera: Add DFL bus driver for Altera API Controller
  spi: altera: separate core code from platform code
  spi: stm32-qspi: Fix compilation warning in ARM64
  spi: Handle SPI device setup callback failure.
  spi: sync up initial chipselect state
  spi: stm32-qspi: Add dirmap support
  spi: stm32-qspi: Trigger DMA only if more than 4 bytes to transfer
  spi: stm32-qspi: fix pm_runtime usage_count counter
  spi: spi-zynqmp-gqspi: return -ENOMEM if dma_map_single fails
  spi: spi-zynqmp-gqspi: fix use-after-free in zynqmp_qspi_exec_op
  spi: spi-zynqmp-gqspi: Resolved slab-out-of-bounds bug
  spi: spi-zynqmp-gqspi: fix hang issue when suspend/resume
  ...
parents ca62e909 86527bcb

Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt

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Broadcom SPI controller



The Broadcom SPI controller is a SPI master found on various SOCs, including

BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits

of :

 MSPI : SPI master controller can read and write to a SPI slave device

 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration

	for flash reads and be configured to do single, double, quad lane

	io with 3-byte and 4-byte addressing support.



 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.

 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance

 of a MSPI master without the BSPI to use with non flash slave devices that

 use SPI protocol.



Required properties:



- #address-cells:

    Must be <1>, as required by generic SPI binding.



- #size-cells:

    Must be <0>, also as required by generic SPI binding.



- compatible:

    Must be one of :

    "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs

    "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI

						   BRCMSTB  SoCs

    "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

                                                                            BRCMSTB  SoCs

    "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"     : MSPI+BSPI on Cygnus, NSP

    "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"     : NS2 SoCs



- reg:

    Define the bases and ranges of the associated I/O address spaces.

    The required range is MSPI controller registers.



- reg-names:

    First name does not matter, but must be reserved for the MSPI controller

    register range as mentioned in 'reg' above, and will typically contain

    - "bspi_regs": BSPI register range, not required with compatible

		   "spi-brcmstb-mspi"

    - "mspi_regs": MSPI register range is required for compatible strings

    - "intr_regs", "intr_status_reg" : Interrupt and status register for

      NSP, NS2, Cygnus SoC



- interrupts

    The interrupts used by the MSPI and/or BSPI controller.



- interrupt-names:

    Names of interrupts associated with MSPI

    - "mspi_halted" :

    - "mspi_done": Indicates that the requested SPI operation is complete.

    - "spi_lr_fullness_reached" : Linear read BSPI pipe full

    - "spi_lr_session_aborted"  : Linear read BSPI pipe aborted

    - "spi_lr_impatient" : Linear read BSPI requested when pipe empty

    - "spi_lr_session_done" : Linear read BSPI session done



- clocks:

    A phandle to the reference clock for this block.



Optional properties:





- native-endian

    Defined when using BE SoC and device uses BE register read/write



Recommended optional m25p80 properties:

- spi-rx-bus-width: Definition as per

                    Documentation/devicetree/bindings/spi/spi-bus.txt



Examples:



BRCMSTB SoC Example:



  SPI Master (MSPI+BSPI) for SPI-NOR access:



    spi@f03e3400 {

		#address-cells = <0x1>;

		#size-cells = <0x0>;

		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";

		reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;

		reg-names = "cs_reg", "mspi", "bspi";

		interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;

		interrupt-parent = <0x1c>;

		interrupt-names = "mspi_halted",

				  "mspi_done",

				  "spi_lr_overread",

				  "spi_lr_session_done",

				  "spi_lr_impatient",

				  "spi_lr_session_aborted",

				  "spi_lr_fullness_reached";



		clocks = <&hif_spi>;

		clock-names = "sw_spi";



		m25p80@0 {

			#size-cells = <0x2>;

			#address-cells = <0x2>;

			compatible = "m25p80";

			reg = <0x0>;

			spi-max-frequency = <0x2625a00>;

			spi-cpol;

			spi-cpha;

			m25p,fast-read;



			flash0.bolt@0 {

				reg = <0x0 0x0 0x0 0x100000>;

			};



			flash0.macadr@100000 {

				reg = <0x0 0x100000 0x0 0x10000>;

			};



			flash0.nvram@110000 {

				reg = <0x0 0x110000 0x0 0x10000>;

			};



			flash0.kernel@120000 {

				reg = <0x0 0x120000 0x0 0x400000>;

			};



			flash0.devtree@520000 {

				reg = <0x0 0x520000 0x0 0x10000>;

			};



			flash0.splash@530000 {

				reg = <0x0 0x530000 0x0 0x80000>;

			};



			flash0@0 {

				reg = <0x0 0x0 0x0 0x4000000>;

			};

		};

	};





    MSPI master for any SPI device :



	spi@f0416000 {

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&upg_fixed>;

		compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";

		reg = <0xf0416000 0x180>;

		reg-names = "mspi";

		interrupts = <0x14>;

		interrupt-parent = <&irq0_aon_intc>;

		interrupt-names = "mspi_done";

	};



iProc SoC Example:



    qspi: spi@18027200 {

	compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";

	reg = <0x18027200 0x184>,

	      <0x18027000 0x124>,

	      <0x1811c408 0x004>,

	      <0x180273a0 0x01c>;

	reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg";

	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names =

		     "spi_lr_fullness_reached",

		     "spi_lr_session_aborted",

		     "spi_lr_impatient",

		     "spi_lr_session_done",

		     "mspi_done",

		     "mspi_halted";

	clocks = <&iprocmed>;

	clock-names = "iprocmed";

	num-cs = <2>;

	#address-cells = <1>;

	#size-cells = <0>;

    };





 NS2 SoC Example:



	       qspi: spi@66470200 {

		       compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";

		       reg = <0x66470200 0x184>,

			     <0x66470000 0x124>,

			     <0x67017408 0x004>,

			     <0x664703a0 0x01c>;

		       reg-names = "mspi", "bspi", "intr_regs",

			"intr_status_reg";

		       interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;

		       interrupt-names = "spi_l1_intr";

			clocks = <&iprocmed>;

			clock-names = "iprocmed";

			num-cs = <2>;

			#address-cells = <1>;

			#size-cells = <0>;

	       };





 m25p80 node for NSP, NS2



	 &qspi {

		      flash: m25p80@0 {

		      #address-cells = <1>;

		      #size-cells = <1>;

		      compatible = "m25p80";

		      reg = <0x0>;

		      spi-max-frequency = <12500000>;

		      m25p,fast-read;

		      spi-cpol;

		      spi-cpha;



		      partition@0 {

				  label = "boot";

				  reg = <0x00000000 0x000a0000>;

		      };



		      partition@a0000 {

				  label = "env";

				  reg = <0x000a0000 0x00060000>;

		      };



		      partition@100000 {

				  label = "system";

				  reg = <0x00100000 0x00600000>;

		      };



		      partition@700000 {

				  label = "rootfs";

				  reg = <0x00700000 0x01900000>;

		      };

	};

Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom SPI controller



maintainers:

  - Kamal Dasu <kdasu.kdev@gmail.com>

  - Rafał Miłecki <rafal@milecki.pl>



description: |

  The Broadcom SPI controller is a SPI master found on various SOCs, including

  BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits

  of:

    MSPI : SPI master controller can read and write to a SPI slave device

    BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration

           for flash reads and be configured to do single, double, quad lane

           io with 3-byte and 4-byte addressing support.



  Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.

  MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance

  of a MSPI master without the BSPI to use with non flash slave devices that

  use SPI protocol.



allOf:

  - $ref: spi-controller.yaml#



properties:

  compatible:

    oneOf:

      - description: Second Instance of MSPI BRCMSTB SoCs

        items:

          - enum:

              - brcm,spi-bcm7425-qspi

              - brcm,spi-bcm7429-qspi

              - brcm,spi-bcm7435-qspi

              - brcm,spi-bcm7445-qspi

              - brcm,spi-bcm7216-qspi

              - brcm,spi-bcm7278-qspi

          - const: brcm,spi-bcm-qspi

          - const: brcm,spi-brcmstb-mspi

      - description: Second Instance of MSPI BRCMSTB SoCs

        items:

          - enum:

              - brcm,spi-brcmstb-qspi

              - brcm,spi-brcmstb-mspi

              - brcm,spi-nsp-qspi

              - brcm,spi-ns2-qspi

          - const: brcm,spi-bcm-qspi



  reg:

    minItems: 1

    maxItems: 5



  reg-names:

    minItems: 1

    maxItems: 5

    items:

      - const: mspi

      - const: bspi

      - enum: [ intr_regs, intr_status_reg, cs_reg ]

      - enum: [ intr_regs, intr_status_reg, cs_reg ]

      - enum: [ intr_regs, intr_status_reg, cs_reg ]



  interrupts:

    minItems: 1

    maxItems: 7



  interrupt-names:

    oneOf:

      - minItems: 1

        maxItems: 7

        items:

          - const: mspi_done

          - const: mspi_halted

          - const: spi_lr_fullness_reached

          - const: spi_lr_session_aborted

          - const: spi_lr_impatient

          - const: spi_lr_session_done

          - const: spi_lr_overread

      - const: spi_l1_intr



  clocks:

    maxItems: 1

    description: reference clock for this block



  native-endian:

    $ref: /schemas/types.yaml#/definitions/flag

    description: Defined when using BE SoC and device uses BE register read/write



unevaluatedProperties: false



required:

  - reg

  - reg-names

  - interrupts

  - interrupt-names



examples:

  - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access

    spi@f03e3400 {

            compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";

            reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;

            reg-names = "mspi", "bspi", "cs_reg";

            interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;

            interrupt-parent = <&gic>;

            interrupt-names = "mspi_done",

                              "mspi_halted",

                              "spi_lr_fullness_reached",

                              "spi_lr_session_aborted",

                              "spi_lr_impatient",

                              "spi_lr_session_done",

                              "spi_lr_overread";

            clocks = <&hif_spi>;

            #address-cells = <0x1>;

            #size-cells = <0x0>;



            flash@0 {

                    #size-cells = <0x2>;

                    #address-cells = <0x2>;

                    compatible = "m25p80";

                    reg = <0x0>;

                    spi-max-frequency = <0x2625a00>;

                    spi-cpol;

                    spi-cpha;

            };

    };

  - | # BRCMSTB SoC: MSPI master for any SPI device

    spi@f0416000 {

            clocks = <&upg_fixed>;

            compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";

            reg = <0xf0416000 0x180>;

            reg-names = "mspi";

            interrupts = <0x14>;

            interrupt-parent = <&irq0_aon_intc>;

            interrupt-names = "mspi_done";

            #address-cells = <1>;

            #size-cells = <0>;

    };

  - | # iProc SoC

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    spi@18027200 {

            compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";

            reg = <0x18027200 0x184>,

                  <0x18027000 0x124>,

                  <0x1811c408 0x004>,

                  <0x180273a0 0x01c>;

            reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";

            interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "mspi_done",

                              "mspi_halted",

                              "spi_lr_fullness_reached",

                              "spi_lr_session_aborted",

                              "spi_lr_impatient",

                              "spi_lr_session_done";

            clocks = <&iprocmed>;

            num-cs = <2>;

            #address-cells = <1>;

            #size-cells = <0>;

    };

  - | # NS2 SoC

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    spi@66470200 {

            compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";

            reg = <0x66470200 0x184>,

                  <0x66470000 0x124>,

                  <0x67017408 0x004>,

                  <0x664703a0 0x01c>;

            reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";

            interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "spi_l1_intr";

            clocks = <&iprocmed>;

            num-cs = <2>;

            #address-cells = <1>;

            #size-cells = <0>;



            flash@0 {

                    #address-cells = <1>;

                    #size-cells = <1>;

                    compatible = "m25p80";

                    reg = <0x0>;

                    spi-max-frequency = <12500000>;

                    spi-cpol;

                    spi-cpha;

            };

    };

Documentation/devicetree/bindings/spi/cadence-quadspi.txt

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* Cadence Quad SPI controller



Required properties:

- compatible : should be one of the following:

	Generic default - "cdns,qspi-nor".

	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".

	For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".

	For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".

- reg : Contains two entries, each of which is a tuple consisting of a

	physical address and length. The first entry is the address and

	length of the controller register set. The second entry is the

	address and length of the QSPI Controller data area.

- interrupts : Unit interrupt specifier for the controller interrupt.

- clocks : phandle to the Quad SPI clock.

- cdns,fifo-depth : Size of the data FIFO in words.

- cdns,fifo-width : Bus width of the data FIFO in bytes.

- cdns,trigger-address : 32-bit indirect AHB trigger address.



Optional properties:

- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.

- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch

  the read data rather than the QSPI clock. Make sure that QSPI return

  clock is populated on the board before using this property.



Optional subnodes:

Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional

custom properties:

- cdns,read-delay : Delay for read capture logic, in clock cycles

- cdns,tshsl-ns : Delay in nanoseconds for the length that the master

                  mode chip select outputs are de-asserted between

		  transactions.

- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being

                  de-activated and the activation of another.

- cdns,tchsh-ns : Delay in nanoseconds between last bit of current

                  transaction and deasserting the device chip select

		  (qspi_n_ss_out).

- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low

                  and first bit transfer.

- resets	: Must contain an entry for each entry in reset-names.

		  See ../reset/reset.txt for details.

- reset-names	: Must include either "qspi" and/or "qspi-ocp".



Example:



	qspi: spi@ff705000 {

		compatible = "cdns,qspi-nor";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xff705000 0x1000>,

		      <0xffa00000 0x1000>;

		interrupts = <0 151 4>;

		clocks = <&qspi_clk>;

		cdns,is-decoded-cs;

		cdns,fifo-depth = <128>;

		cdns,fifo-width = <4>;

		cdns,trigger-address = <0x00000000>;

		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;

		reset-names = "qspi", "qspi-ocp";



		flash0: n25q00@0 {

			...

			cdns,read-delay = <4>;

			cdns,tshsl-ns = <50>;

			cdns,tsd2d-ns = <50>;

			cdns,tchsh-ns = <4>;

			cdns,tslch-ns = <4>;

		};

	};

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cadence Quad SPI controller



maintainers:

  - Pratyush Yadav <p.yadav@ti.com>



allOf:

  - $ref: spi-controller.yaml#



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - ti,k2g-qspi

              - ti,am654-ospi

              - intel,lgm-qspi

          - const: cdns,qspi-nor

      - const: cdns,qspi-nor



  reg:

    items:

      - description: the controller register set

      - description: the controller data area



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  cdns,fifo-depth:

    description:

      Size of the data FIFO in words.

    $ref: "/schemas/types.yaml#/definitions/uint32"

    enum: [ 128, 256 ]

    default: 128



  cdns,fifo-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Bus width of the data FIFO in bytes.

    default: 4



  cdns,trigger-address:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      32-bit indirect AHB trigger address.



  cdns,is-decoded-cs:

    type: boolean

    description:

      Flag to indicate whether decoder is used to select different chip select

      for different memory regions.



  cdns,rclk-en:

    type: boolean

    description:

      Flag to indicate that QSPI return clock is used to latch the read

      data rather than the QSPI clock. Make sure that QSPI return clock

      is populated on the board before using this property.



  resets:

    maxItems: 2



  reset-names:

    minItems: 1

    maxItems: 2

    items:

      enum: [ qspi, qspi-ocp ]



# subnode's properties

patternProperties:

  "@[0-9a-f]+$":

    type: object

    description:

      Flash device uses the below defined properties in the subnode.



    properties:

      cdns,read-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay for read capture logic, in clock cycles.



      cdns,tshsl-ns:

        description:

          Delay in nanoseconds for the length that the master mode chip select

          outputs are de-asserted between transactions.



      cdns,tsd2d-ns:

        description:

          Delay in nanoseconds between one chip select being de-activated

          and the activation of another.



      cdns,tchsh-ns:

        description:

          Delay in nanoseconds between last bit of current transaction and

          deasserting the device chip select (qspi_n_ss_out).



      cdns,tslch-ns:

        description:

          Delay in nanoseconds between setting qspi_n_ss_out low and

          first bit transfer.



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - cdns,fifo-depth

  - cdns,fifo-width

  - cdns,trigger-address

  - '#address-cells'

  - '#size-cells'



unevaluatedProperties: false



examples:

  - |

    qspi: spi@ff705000 {

      compatible = "cdns,qspi-nor";

      #address-cells = <1>;

      #size-cells = <0>;

      reg = <0xff705000 0x1000>,

            <0xffa00000 0x1000>;

      interrupts = <0 151 4>;

      clocks = <&qspi_clk>;

      cdns,fifo-depth = <128>;

      cdns,fifo-width = <4>;

      cdns,trigger-address = <0x00000000>;

      resets = <&rst 0x1>, <&rst 0x2>;

      reset-names = "qspi", "qspi-ocp";



      flash@0 {

              compatible = "jedec,spi-nor";

              reg = <0x0>;

      };

    };

Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Quad Serial Peripheral Interface (QuadSPI)



maintainers:

  - Han Xu <han.xu@nxp.com>



allOf:

  - $ref: "spi-controller.yaml#"



properties:

  compatible:

    oneOf:

      - enum:

          - fsl,vf610-qspi

          - fsl,imx6sx-qspi

          - fsl,imx7d-qspi

          - fsl,imx6ul-qspi

          - fsl,ls1021a-qspi

          - fsl,ls2080a-qspi

      - items:

          - enum:

              - fsl,ls1043a-qspi

          - const: fsl,ls1021a-qspi

      - items:

          - enum:

              - fsl,imx8mq-qspi

          - const: fsl,imx7d-qspi



  reg:

    items:

      - description: registers

      - description: memory mapping



  reg-names:

    items:

      - const: QuadSPI

      - const: QuadSPI-memory



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: SoC SPI qspi_en clock

      - description: SoC SPI qspi clock



  clock-names:

    items:

      - const: qspi_en

      - const: qspi



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        spi@1550000 {

            compatible = "fsl,ls1021a-qspi";

            reg = <0x0 0x1550000 0x0 0x100000>,

                  <0x0 0x40000000 0x0 0x10000000>;

            reg-names = "QuadSPI", "QuadSPI-memory";

            interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

            #address-cells = <1>;

            #size-cells = <0>;

            clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,

                     <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;

            clock-names = "qspi_en", "qspi";



            flash@0 {

                compatible = "jedec,spi-nor";

                spi-max-frequency = <50000000>;

                reg = <0>;

                spi-rx-bus-width = <4>;

                spi-tx-bus-width = <4>;

            };

        };

    };