Commit 49e3d8ea authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/fsl_booke: Enable STRICT_KERNEL_RWX 



Enable STRICT_KERNEL_RWX on fsl_booke.

For that, we need additional TLBCAMs dedicated to linear mapping,
based on the alignment of _sinittext.

By default, up to 768 Mbytes of memory are mapped.
It uses 3 TLBCAMs of size 256 Mbytes.

With a data alignment of 16, we need up to 9 TLBCAMs:
  16/16/16/16/64/64/64/256/256

With a data alignment of 4, we need up to 12 TLBCAMs:
  4/4/4/4/16/16/16/64/64/64/256/256

With a data alignment of 1, we need up to 15 TLBCAMs:
  1/1/1/1/4/4/4/16/16/16/64/64/64/256/256

By default, set a 16 Mbytes alignment as a compromise between memory
usage and number of TLBCAMs. This can be adjusted manually when needed.

For the time being, it doens't work when the base is randomised.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/29f9e5d2bbbc83ae9ca879265426a6278bf4d5bb.1634292136.git.christophe.leroy@csgroup.eu
parent d5970045

arch/powerpc/Kconfig

+9 −2
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ config PPC 
	select ARCH_HAS_SCALED_CPUTIME		if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64

	select ARCH_HAS_SET_MEMORY

	select ARCH_HAS_STRICT_KERNEL_RWX	if (PPC_BOOK3S || PPC_8xx || 40x) && !HIBERNATION

	select ARCH_HAS_STRICT_KERNEL_RWX	if FSL_BOOKE && !HIBERNATION && !RANDOMIZE_BASE

	select ARCH_HAS_STRICT_MODULE_RWX	if ARCH_HAS_STRICT_KERNEL_RWX && !PPC_BOOK3S_32

	select ARCH_HAS_TICK_BROADCAST		if GENERIC_CLOCKEVENTS_BROADCAST

	select ARCH_HAS_UACCESS_FLUSHCACHE
@@ -778,7 +779,8 @@ config DATA_SHIFT_BOOL 
	bool "Set custom data alignment"

	depends on ADVANCED_OPTIONS

	depends on STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE

	depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && !STRICT_KERNEL_RWX)

	depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && !STRICT_KERNEL_RWX) || \

		   FSL_BOOKE

	help

	  This option allows you to set the kernel data alignment. When

	  RAM is mapped by blocks, the alignment needs to fit the size and
@@ -791,11 +793,13 @@ config DATA_SHIFT 
	default 24 if STRICT_KERNEL_RWX && PPC64

	range 17 28 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_BOOK3S_32

	range 19 23 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_8xx

	range 20 24 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_FSL_BOOKE

	default 22 if STRICT_KERNEL_RWX && PPC_BOOK3S_32

	default 18 if (DEBUG_PAGEALLOC || KFENCE) && PPC_BOOK3S_32

	default 23 if STRICT_KERNEL_RWX && PPC_8xx

	default 23 if (DEBUG_PAGEALLOC || KFENCE) && PPC_8xx && PIN_TLB_DATA

	default 19 if (DEBUG_PAGEALLOC || KFENCE) && PPC_8xx

	default 24 if STRICT_KERNEL_RWX && FSL_BOOKE

	default PPC_PAGE_SHIFT

	help

	  On Book3S 32 (603+), DBATs are used to map kernel text and rodata RO.
@@ -1123,7 +1127,10 @@ config LOWMEM_CAM_NUM_BOOL 
config LOWMEM_CAM_NUM

	depends on FSL_BOOKE

	int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL

	default 3

	default 3 if !STRICT_KERNEL_RWX

	default 9 if DATA_SHIFT >= 24

	default 12 if DATA_SHIFT >= 22

	default 15



config DYNAMIC_MEMSTART

	bool "Enable page aligned dynamic load address for kernel"