Commit 49e2eb55 authored by Jing Li's avatar Jing Li Committed by guzitao
Browse files

sw64: pci: adjust the maximum number of RC per node 

Sunway inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB73UR



--------------------------------

Adjust the maximum number of RC per node from 6 to 12, since the
upcoming hardware platform supports 12 RC per node.

This commit also update the OEM table ID of MCFG.

Signed-off-by: default avatarJing Li <jingli@wxiat.com>
Reviewed-by: default avatarHe Sheng <hesheng@wxiat.com>
Signed-off-by: default avatarGu Zitao <guzitao@wxiat.com>
parent c0d60a8d

arch/sw_64/include/asm/pci.h

+3 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ extern int sw64_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 
		int where, int size, u32 *val);



extern void pci_mark_rc_linkup(unsigned long node, unsigned long index);

extern void pci_clear_rc_linkup(unsigned long node, unsigned long index);

extern int pci_get_rc_linkup(unsigned long node, unsigned long index);



#ifdef CONFIG_PCI_DOMAINS
@@ -171,4 +172,6 @@ extern int chip_pcie_configure(struct pci_controller *hose); 


#define PCITODMA_OFFSET			0x0	/*0 offset*/



#define MAX_NR_RCS_PER_NODE		12



#endif /* _ASM_SW64_PCI_H */

arch/sw_64/include/asm/uncore_io_junzhang.h

+0 −3
Original line number Diff line number Diff line
@@ -48,9 +48,6 @@ 
#define SW64_PCI0_BUS		0

#define PCI0_BUS		SW64_PCI0_BUS



#define MAX_NR_NODES		0x2

#define MAX_NR_RCS		0x6



#define SPBU_BASE		(0x3UL << 36)

#define INTPU_BASE		(0x3aUL << 32)

#define IIC0_BASE		(0x31UL << 32)

arch/sw_64/include/asm/uncore_io_xuelang.h

+0 −3
Original line number Diff line number Diff line
@@ -47,9 +47,6 @@ 
#define SW64_PCI0_BUS		0

#define PCI0_BUS		SW64_PCI0_BUS



#define MAX_NR_NODES		0x2

#define MAX_NR_RCS		0x6



#define MCU_BASE		(0x3UL << 36)

#define CAB0_BASE		(0x10UL << 32)

#define INTPU_BASE		(0x2aUL << 32)

arch/sw_64/pci/pci-legacy.c

+3 −3
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static bool __init is_any_rc_linkup_one_node(unsigned long node) 
{

	int i;



	for (i = 0; i < 8; ++i) {

	for (i = 0; i < MAX_NR_RCS_PER_NODE; ++i) {

		if (pci_get_rc_linkup(node, i))

			return true;

	}
@@ -279,14 +279,14 @@ void __init sw64_init_arch(void) 
				pr_notice("PCIe is disabled on node %ld\n", node);

				continue;

			}

			for (i = 0; i < MAX_NR_RCS; i++) {

			for (i = 0; i < MAX_NR_RCS_PER_NODE; i++) {

				if ((rc_enable >> i) & 0x1)

					sw64_init_host(node, i);

			}

			if (is_any_rc_linkup_one_node(node)) {

				memset(msg, 0, 64);

				sprintf(msg, "Node %ld: RC [ ", node);

				for (i = 0; i < MAX_NR_RCS; i++) {

				for (i = 0; i < MAX_NR_RCS_PER_NODE; i++) {

					if (pci_get_rc_linkup(node, i)) {

						memset(id, 0, 8);

						sprintf(id, "%d ", i);

drivers/acpi/pci_mcfg.c

+23 −23
Original line number Diff line number Diff line
@@ -201,29 +201,29 @@ static struct mcfg_fixup mcfg_quirks[] = { 
#endif /* LOONGARCH */



#ifdef CONFIG_SW64

#define _SW64_ECAM_QUIRK(rev, seg) \

	{ "SUNWAY", "MCFG", rev, seg, MCFG_BUS_ANY, &sw64_pci_ecam_ops }

#define SW64_ECAM_QUIRK(rev, node)	_SW64_ECAM_QUIRK(rev, node * 8 + 0),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 1),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 2),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 3),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 4),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 5),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 6),\

					_SW64_ECAM_QUIRK(rev, node * 8 + 7)



	/**

	 * According to the address space of sw64, up to 8 nodes supported

	 * with a maximum of 8 pcie controllers per node

	 */

	SW64_ECAM_QUIRK(1, 0x00),

	SW64_ECAM_QUIRK(1, 0x01),

	SW64_ECAM_QUIRK(1, 0x02),

	SW64_ECAM_QUIRK(1, 0x03),

	SW64_ECAM_QUIRK(1, 0x04),

	SW64_ECAM_QUIRK(1, 0x05),

	SW64_ECAM_QUIRK(1, 0x06),

	SW64_ECAM_QUIRK(1, 0x07),

#define SW64_ECAM_QUIRK(table_id, rev, node, ops) \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 0),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 1),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 2),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 3),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 4),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 5),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 6),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 7),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 8),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 9),  MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 10), MCFG_BUS_ANY, ops }, \

	{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 11), MCFG_BUS_ANY, ops }  \



	/* up to 8 nodes for SW64 series */

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x00, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x01, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x02, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x03, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x04, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x05, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x06, &sw64_pci_ecam_ops),

	SW64_ECAM_QUIRK("SUNWAY  ", 1, 0x07, &sw64_pci_ecam_ops),

#endif /* SW64 */

};