Merge branches 'iommu/fixes', 'arm/mediatek', 'arm/smmu', 'arm/exynos',... (49d11527) · Commits · EulixOS / Software / Kernel

Documentation/admin-guide/kernel-parameters.txt

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		@@ -1869,13 +1869,6 @@
		bypassed by not enabling DMAR with this option. In
		this case, gfx device will use physical address for
		DMA.
		forcedac [X86-64]
		With this option iommu will not optimize to look
		for io virtual address below 32-bit forcing dual
		address cycle on pci bus for cards supporting greater
		than 32-bit addressing. The default is to look
		for translation below 32-bit and if not available
		then look in the higher range.
		strict [Default Off]
		With this option on every unmap_single operation will
		result in a hardware IOTLB flush operation as opposed
		@@ -1964,6 +1957,14 @@
		nobypass [PPC/POWERNV]
		Disable IOMMU bypass, using IOMMU for PCI devices.

		iommu.forcedac= [ARM64, X86] Control IOVA allocation for PCI devices.
		Format: { "0" \| "1" }
		0 - Try to allocate a 32-bit DMA address first, before
		falling back to the full range if needed.
		1 - Allocate directly from the full usable range,
		forcing Dual Address Cycle for PCI cards supporting
		greater than 32-bit addressing.

		iommu.strict= [ARM64] Configure TLB invalidation behaviour
		Format: { "0" \| "1" }
		0 - Lazy mode.

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0 → 100644

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		# Copyright 2020 Unisoc Inc.
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Unisoc IOMMU and Multi-media MMU

		maintainers:
		- Chunyan Zhang <zhang.lyra@gmail.com>

		properties:
		compatible:
		enum:
		- sprd,iommu-v1

		"#iommu-cells":
		const: 0
		description:
		Unisoc IOMMUs are all single-master IOMMU devices, therefore no
		additional information needs to associate with its master device.
		Please refer to the generic bindings document for more details,
		Documentation/devicetree/bindings/iommu/iommu.txt

		reg:
		maxItems: 1

		clocks:
		description:
		Reference to a gate clock phandle, since access to some of IOMMUs are
		controlled by gate clock, but this is not required.

		required:
		- compatible
		- reg
		- "#iommu-cells"

		additionalProperties: false

		examples:
		- \|
		iommu_disp: iommu@63000800 {
		compatible = "sprd,iommu-v1";
		reg = <0x63000800 0x80>;
		#iommu-cells = <0>;
		};

		- \|
		iommu_jpg: iommu@62300300 {
		compatible = "sprd,iommu-v1";
		reg = <0x62300300 0x80>;
		#iommu-cells = <0>;
		clocks = <&mm_gate 1>;
		};

		...

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		@@ -7,6 +7,8 @@
		#ifndef __FSL_PAMU_STASH_H
		#define __FSL_PAMU_STASH_H

		struct iommu_domain;

		/* cache stash targets */
		enum pamu_stash_target {
		PAMU_ATTR_CACHE_L1 = 1,
		@@ -14,14 +16,6 @@ enum pamu_stash_target {
		PAMU_ATTR_CACHE_L3,
		};

		/*
		* This attribute allows configuring stashig specific parameters
		* in the PAMU hardware.
		*/

		struct pamu_stash_attribute {
		u32 cpu; /* cpu number */
		u32 cache; /* cache to stash to: L1,L2,L3 */
		};
		int fsl_pamu_configure_l1_stash(struct iommu_domain *domain, u32 cpu);

		#endif /* __FSL_PAMU_STASH_H */

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