Commit 49be4fb2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.3-1-2023-03-09' of... 

Merge tag 'perf-tools-fixes-for-v6.3-1-2023-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull perf tools fixes from Arnaldo Carvalho de Melo:

 - Add Adrian Hunter to MAINTAINERS as a perf tools reviewer

 - Sync various tools/ copies of kernel headers with the kernel sources,
   this time trying to avoid first merging with upstream to then update
   but instead copy from upstream so that a merge is avoided and the end
   result after merging this pull request is the one expected,
   tools/perf/check-headers.sh (mostly) happy, less warnings while
   building tools/perf/

 - Fix counting when initial delay configured by setting
   perf_attr.enable_on_exec when starting workloads from the perf
   command line

 - Don't avoid emitting a PERF_RECORD_MMAP2 in 'perf inject
   --buildid-all' when that record comes with a build-id, otherwise we
   end up not being able to resolve symbols

 - Don't use comma as the CSV output separator the "stat+csv_output"
   test, as comma can appear on some tests as a modifier for an event,
   use @ instead, ditto for the JSON linter test

 - The offcpu test was looking for some bits being set on
   task_struct->prev_state without masking other bits not important for
   this specific 'perf test', fix it

* tag 'perf-tools-fixes-for-v6.3-1-2023-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux:
  perf tools: Add Adrian Hunter to MAINTAINERS as a reviewer
  tools headers UAPI: Sync linux/perf_event.h with the kernel sources
  tools headers x86 cpufeatures: Sync with the kernel sources
  tools include UAPI: Sync linux/vhost.h with the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  tools headers kvm: Sync uapi/{asm/linux} kvm.h headers with the kernel sources
  tools include UAPI: Synchronize linux/fcntl.h with the kernel sources
  tools headers: Synchronize {linux,vdso}/bits.h with the kernel sources
  tools headers UAPI: Sync linux/prctl.h with the kernel sources
  tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench'
  perf stat: Fix counting when initial delay configured
  tools headers svm: Sync svm headers with the kernel sources
  perf test: Avoid counting commas in json linter
  perf tests stat+csv_output: Switch CSV separator to @
  perf inject: Fix --buildid-all not to eat up MMAP2
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  perf test: Fix offcpu test prev_state check
parents 44889ba5 5b201a82

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -16391,6 +16391,7 @@ R: Alexander Shishkin <alexander.shishkin@linux.intel.com> 
R:	Jiri Olsa <jolsa@kernel.org>

R:	Namhyung Kim <namhyung@kernel.org>

R:	Ian Rogers <irogers@google.com>

R:	Adrian Hunter <adrian.hunter@intel.com>

L:	linux-perf-users@vger.kernel.org

L:	linux-kernel@vger.kernel.org

S:	Supported

tools/arch/arm64/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ struct kvm_regs { 
#define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */

#define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */

#define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */

#define KVM_ARM_VCPU_HAS_EL2		7 /* Support nested virtualization */



struct kvm_vcpu_init {

	__u32 target;

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS			20	   /* N 32-bit words worth of info */

#define NCAPINTS			21	   /* N 32-bit words worth of info */

#define NBUGINTS			1	   /* N 32-bit bug flags */



/*

tools/arch/x86/include/asm/disabled-features.h

+2 −1
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ 
#define DISABLED_MASK17	0

#define DISABLED_MASK18	0

#define DISABLED_MASK19	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)

#define DISABLED_MASK20	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)



#endif /* _ASM_X86_DISABLED_FEATURES_H */

tools/arch/x86/include/asm/msr-index.h

+31 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define _EFER_SVME		12 /* Enable virtualization */

#define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */

#define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */

#define _EFER_AUTOIBRS		21 /* Enable Automatic IBRS */



#define EFER_SCE		(1<<_EFER_SCE)

#define EFER_LME		(1<<_EFER_LME)
@@ -33,6 +34,7 @@ 
#define EFER_SVME		(1<<_EFER_SVME)

#define EFER_LMSLE		(1<<_EFER_LMSLE)

#define EFER_FFXSR		(1<<_EFER_FFXSR)

#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)



/* Intel MSRs. Some also available on other CPUs */
@@ -49,6 +51,10 @@ 
#define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */

#define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)



/* A mask for bits which the kernel toggles when controlling mitigations */

#define SPEC_CTRL_MITIGATIONS_MASK	(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \

							| SPEC_CTRL_RRSBA_DIS_S)



#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */

#define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
@@ -189,6 +195,9 @@ 
#define MSR_TURBO_RATIO_LIMIT1		0x000001ae

#define MSR_TURBO_RATIO_LIMIT2		0x000001af



#define MSR_SNOOP_RSP_0			0x00001328

#define MSR_SNOOP_RSP_1			0x00001329



#define MSR_LBR_SELECT			0x000001c8

#define MSR_LBR_TOS			0x000001c9
@@ -566,6 +575,26 @@ 
#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)

#define MSR_AMD64_SEV_SNP_ENABLED	BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)



/* SNP feature bits enabled by the hypervisor */

#define MSR_AMD64_SNP_VTOM			BIT_ULL(3)

#define MSR_AMD64_SNP_REFLECT_VC		BIT_ULL(4)

#define MSR_AMD64_SNP_RESTRICTED_INJ		BIT_ULL(5)

#define MSR_AMD64_SNP_ALT_INJ			BIT_ULL(6)

#define MSR_AMD64_SNP_DEBUG_SWAP		BIT_ULL(7)

#define MSR_AMD64_SNP_PREVENT_HOST_IBS		BIT_ULL(8)

#define MSR_AMD64_SNP_BTB_ISOLATION		BIT_ULL(9)

#define MSR_AMD64_SNP_VMPL_SSS			BIT_ULL(10)

#define MSR_AMD64_SNP_SECURE_TSC		BIT_ULL(11)

#define MSR_AMD64_SNP_VMGEXIT_PARAM		BIT_ULL(12)

#define MSR_AMD64_SNP_IBS_VIRT			BIT_ULL(14)

#define MSR_AMD64_SNP_VMSA_REG_PROTECTION	BIT_ULL(16)

#define MSR_AMD64_SNP_SMT_PROTECTION		BIT_ULL(17)



/* SNP feature bits reserved for future use. */

#define MSR_AMD64_SNP_RESERVED_BIT13		BIT_ULL(13)

#define MSR_AMD64_SNP_RESERVED_BIT15		BIT_ULL(15)

#define MSR_AMD64_SNP_RESERVED_MASK		GENMASK_ULL(63, 18)



#define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f



/* AMD Collaborative Processor Performance Control MSRs */
@@ -1061,6 +1090,8 @@ 


/* - AMD: */

#define MSR_IA32_MBA_BW_BASE		0xc0000200

#define MSR_IA32_SMBA_BW_BASE		0xc0000280

#define MSR_IA32_EVT_CFG_BASE		0xc0000400



/* MSR_IA32_VMX_MISC bits */

#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)