Commit 4998897b authored by Rob Herring's avatar Rob Herring Committed by Will Deacon
Browse files

perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event 



Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of
the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the
additional event.

Tested-by: default avatarJames Clark <james.clark@arm.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v4-6-327f860daf28@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 05e4c88e

arch/arm64/include/asm/sysreg.h

+2 −0
Original line number Diff line number Diff line
@@ -221,6 +221,8 @@ 
	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))

#define PMSEVFR_EL1_RES0_V1P1	\

	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))

#define PMSEVFR_EL1_RES0_V1P2	\

	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))



/* Buffer error reporting */

#define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT

drivers/perf/arm_spe_pmu.c

+3 −1
Original line number Diff line number Diff line
@@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) 
	case ID_AA64DFR0_EL1_PMSVer_IMP:

		return PMSEVFR_EL1_RES0_IMP;

	case ID_AA64DFR0_EL1_PMSVer_V1P1:

		return PMSEVFR_EL1_RES0_V1P1;

	case ID_AA64DFR0_EL1_PMSVer_V1P2:

	/* Return the highest version we support in default */

	default:

		return PMSEVFR_EL1_RES0_V1P1;

		return PMSEVFR_EL1_RES0_V1P2;

	}

}