Commit 498d46fe authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: increase bad page number for umc ras query 



One piece of umc normalizing address can be mapped to 16 pieces of
physical address in each umc channel on ALDEBARAN.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 400013b2

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -1213,7 +1213,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 
		adev->umc.ras = &umc_v6_1_ras;

		break;

	case IP_VERSION(6, 7, 0):

		adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;

		adev->umc.max_ras_err_cnt_per_query =

			UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;

		adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;

		adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;

		adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;

drivers/gpu/drm/amd/amdgpu/umc_v6_7.h

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ 
#define UMC_V6_7_CHANNEL_INSTANCE_NUM		8

/* total channel instances in one umc block */

#define UMC_V6_7_TOTAL_CHANNEL_NUM	(UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)

/* one piece of normalizing address is mapped to 8 pieces of physical address */

#define UMC_V6_7_NA_MAP_PA_NUM	8

/* R14 bit shift should be considered, double the number */

#define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL	(UMC_V6_7_NA_MAP_PA_NUM * 2)

/* UMC regiser per channel offset */

#define UMC_V6_7_PER_CHANNEL_OFFSET		0x400

extern struct amdgpu_umc_ras umc_v6_7_ras;