Commit 49890d9c authored by Manikanta Pubbisetty's avatar Manikanta Pubbisetty Committed by Kalle Valo
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ath11k: HAL changes to support WCN6750 



Add HAL changes required to support WCN6750. Offsets of some registers
for WCN6750 are different from other supported devices; move such
register offsets to platform specific ath11k_hw_regs.

Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1

Signed-off-by: default avatarManikanta Pubbisetty <quic_mpubbise@quicinc.com>
Signed-off-by: default avatarKalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20220429170502.20080-8-quic_mpubbise@quicinc.com
parent 73d3e713

drivers/net/wireless/ath/ath11k/core.c

+2 −0
Original line number Diff line number Diff line
@@ -491,8 +491,10 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { 
		},

		.max_radios = 1,

		.bdf_addr = 0x4B0C0000,

		.hw_ops = &wcn6750_ops,

		.ring_mask = &ath11k_hw_ring_mask_qca6390,

		.internal_sleep_clock = false,

		.regs = &wcn6750_regs,

		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,

		.host_ce_config = ath11k_host_ce_config_qca6390,

		.ce_count = 9,

drivers/net/wireless/ath/ath11k/hal.c

+8 −7
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause-Clear

/*

 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */

#include <linux/dma-mapping.h>

#include "hal_tx.h"
@@ -1082,10 +1083,10 @@ static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab, 
	srng = &hal->srng_list[ring_id];



	if (srng_config->ring_dir == HAL_SRNG_DIR_DST)

		srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +

		srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +

						   (unsigned long)ab->mem);

	else

		srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +

		srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +

						   (unsigned long)ab->mem);

}
@@ -1120,7 +1121,7 @@ int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 
	ath11k_dbg(ab, ATH11k_DBG_HAL,

		   "target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d",

		  target_reg,

		  HAL_SHADOW_REG(shadow_cfg_idx),

		  HAL_SHADOW_REG(ab, shadow_cfg_idx),

		  shadow_cfg_idx,

		  ring_type, ring_num);
@@ -1193,12 +1194,12 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab) 
	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab);



	s = &hal->srng_config[HAL_REO_REINJECT];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB;

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab);



	s = &hal->srng_config[HAL_REO_CMD];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB;

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab);



	s = &hal->srng_config[HAL_REO_STATUS];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);

drivers/net/wireless/ath/ath11k/hal.h

+9 −6
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: BSD-3-Clause-Clear */

/*

 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef ATH11K_HAL_H
@@ -31,12 +32,12 @@ struct ath11k_base; 
#define HAL_DSCP_TID_TBL_SIZE			24



/* calculate the register address from bar0 of shadow register x */

#define HAL_SHADOW_BASE_ADDR			0x000008fc

#define HAL_SHADOW_BASE_ADDR(ab)		ab->hw_params.regs->hal_shadow_base_addr

#define HAL_SHADOW_NUM_REGS			36

#define HAL_HP_OFFSET_IN_REG_START		1

#define HAL_OFFSET_FROM_HP_TO_TP		4



#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))

#define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x)))



/* WCSS Relative address */

#define HAL_SEQ_WCSS_UMAC_OFFSET		0x00a00000
@@ -180,16 +181,18 @@ struct ath11k_base; 
#define HAL_REO_TCL_RING_HP(ab)			ab->hw_params.regs->hal_reo_tcl_ring_hp



/* REO CMD R0 address */

#define HAL_REO_CMD_RING_BASE_LSB		0x00000194

#define HAL_REO_CMD_RING_BASE_LSB(ab) \

	ab->hw_params.regs->hal_reo_cmd_ring_base_lsb



/* REO CMD R2 address */

#define HAL_REO_CMD_HP				0x00003020

#define HAL_REO_CMD_HP(ab)			ab->hw_params.regs->hal_reo_cmd_ring_hp



/* SW2REO R0 address */

#define HAL_SW2REO_RING_BASE_LSB		0x000001ec

#define HAL_SW2REO_RING_BASE_LSB(ab) \

	ab->hw_params.regs->hal_sw2reo_ring_base_lsb



/* SW2REO R2 address */

#define HAL_SW2REO_RING_HP			0x00003028

#define HAL_SW2REO_RING_HP(ab)			ab->hw_params.regs->hal_sw2reo_ring_hp



/* CE ring R0 address */

#define HAL_CE_DST_RING_BASE_LSB		0x00000000

drivers/net/wireless/ath/ath11k/hw.c

+134 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause-Clear

/*

 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/types.h>
@@ -1014,6 +1015,13 @@ const struct ath11k_hw_ops wcn6855_ops = { 
	.rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,

};



const struct ath11k_hw_ops wcn6750_ops = {

	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,

	.wmi_init_config = ath11k_init_wmi_config_qca6390,

	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,

	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,

};



#define ATH11K_TX_RING_MASK_0 0x1

#define ATH11K_TX_RING_MASK_1 0x2

#define ATH11K_TX_RING_MASK_2 0x4
@@ -1908,10 +1916,18 @@ const struct ath11k_hw_regs ipq8074_regs = { 
	.hal_reo_tcl_ring_base_lsb = 0x000003fc,

	.hal_reo_tcl_ring_hp = 0x00003058,



	/* REO CMD ring address */

	.hal_reo_cmd_ring_base_lsb = 0x00000194,

	.hal_reo_cmd_ring_hp = 0x00003020,



	/* REO status address */

	.hal_reo_status_ring_base_lsb = 0x00000504,

	.hal_reo_status_hp = 0x00003070,



	/* SW2REO ring address */

	.hal_sw2reo_ring_base_lsb = 0x000001ec,

	.hal_sw2reo_ring_hp = 0x00003028,



	/* WCSS relative address */

	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,

	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
@@ -1932,6 +1948,9 @@ const struct ath11k_hw_regs ipq8074_regs = { 
	/* PCIe base address */

	.pcie_qserdes_sysclk_en_sel = 0x0,

	.pcie_pcs_osc_dtct_config_base = 0x0,



	/* Shadow register area */

	.hal_shadow_base_addr = 0x0,

};



const struct ath11k_hw_regs qca6390_regs = {
@@ -1979,10 +1998,18 @@ const struct ath11k_hw_regs qca6390_regs = { 
	.hal_reo_tcl_ring_base_lsb = 0x000003a4,

	.hal_reo_tcl_ring_hp = 0x00003050,



	/* REO CMD ring address */

	.hal_reo_cmd_ring_base_lsb = 0x00000194,

	.hal_reo_cmd_ring_hp = 0x00003020,



	/* REO status address */

	.hal_reo_status_ring_base_lsb = 0x000004ac,

	.hal_reo_status_hp = 0x00003068,



	/* SW2REO ring address */

	.hal_sw2reo_ring_base_lsb = 0x000001ec,

	.hal_sw2reo_ring_hp = 0x00003028,



	/* WCSS relative address */

	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,

	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
@@ -2003,6 +2030,9 @@ const struct ath11k_hw_regs qca6390_regs = { 
	/* PCIe base address */

	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,

	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,



	/* Shadow register area */

	.hal_shadow_base_addr = 0x000008fc,

};



const struct ath11k_hw_regs qcn9074_regs = {
@@ -2050,10 +2080,18 @@ const struct ath11k_hw_regs qcn9074_regs = { 
	.hal_reo_tcl_ring_base_lsb = 0x000003fc,

	.hal_reo_tcl_ring_hp = 0x00003058,



	/* REO CMD ring address */

	.hal_reo_cmd_ring_base_lsb = 0x00000194,

	.hal_reo_cmd_ring_hp = 0x00003020,



	/* REO status address */

	.hal_reo_status_ring_base_lsb = 0x00000504,

	.hal_reo_status_hp = 0x00003070,



	/* SW2REO ring address */

	.hal_sw2reo_ring_base_lsb = 0x000001ec,

	.hal_sw2reo_ring_hp = 0x00003028,



	/* WCSS relative address */

	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,

	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
@@ -2074,6 +2112,9 @@ const struct ath11k_hw_regs qcn9074_regs = { 
	/* PCIe base address */

	.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,

	.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,



	/* Shadow register area */

	.hal_shadow_base_addr = 0x0,

};



const struct ath11k_hw_regs wcn6855_regs = {
@@ -2121,10 +2162,18 @@ const struct ath11k_hw_regs wcn6855_regs = { 
	.hal_reo_tcl_ring_base_lsb = 0x00000454,

	.hal_reo_tcl_ring_hp = 0x00003060,



	/* REO CMD ring address */

	.hal_reo_cmd_ring_base_lsb = 0x00000194,

	.hal_reo_cmd_ring_hp = 0x00003020,



	/* REO status address */

	.hal_reo_status_ring_base_lsb = 0x0000055c,

	.hal_reo_status_hp = 0x00003078,



	/* SW2REO ring address */

	.hal_sw2reo_ring_base_lsb = 0x000001ec,

	.hal_sw2reo_ring_hp = 0x00003028,



	/* WCSS relative address */

	.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,

	.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
@@ -2145,6 +2194,91 @@ const struct ath11k_hw_regs wcn6855_regs = { 
	/* PCIe base address */

	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,

	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,



	/* Shadow register area */

	.hal_shadow_base_addr = 0x000008fc,

};



const struct ath11k_hw_regs wcn6750_regs = {

	/* SW2TCL(x) R0 ring configuration address */

	.hal_tcl1_ring_base_lsb = 0x00000694,

	.hal_tcl1_ring_base_msb = 0x00000698,

	.hal_tcl1_ring_id = 0x0000069c,

	.hal_tcl1_ring_misc = 0x000006a4,

	.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,

	.hal_tcl1_ring_tp_addr_msb = 0x000006b4,

	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,

	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,

	.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,

	.hal_tcl1_ring_msi1_base_msb = 0x000006e0,

	.hal_tcl1_ring_msi1_data = 0x000006e4,

	.hal_tcl2_ring_base_lsb = 0x000006ec,

	.hal_tcl_ring_base_lsb = 0x0000079c,



	/* TCL STATUS ring address */

	.hal_tcl_status_ring_base_lsb = 0x000008a4,



	/* REO2SW(x) R0 ring configuration address */

	.hal_reo1_ring_base_lsb = 0x000001ec,

	.hal_reo1_ring_base_msb = 0x000001f0,

	.hal_reo1_ring_id = 0x000001f4,

	.hal_reo1_ring_misc = 0x000001fc,

	.hal_reo1_ring_hp_addr_lsb = 0x00000200,

	.hal_reo1_ring_hp_addr_msb = 0x00000204,

	.hal_reo1_ring_producer_int_setup = 0x00000210,

	.hal_reo1_ring_msi1_base_lsb = 0x00000234,

	.hal_reo1_ring_msi1_base_msb = 0x00000238,

	.hal_reo1_ring_msi1_data = 0x0000023c,

	.hal_reo2_ring_base_lsb = 0x00000244,

	.hal_reo1_aging_thresh_ix_0 = 0x00000564,

	.hal_reo1_aging_thresh_ix_1 = 0x00000568,

	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,

	.hal_reo1_aging_thresh_ix_3 = 0x00000570,



	/* REO2SW(x) R2 ring pointers (head/tail) address */

	.hal_reo1_ring_hp = 0x00003028,

	.hal_reo1_ring_tp = 0x0000302c,

	.hal_reo2_ring_hp = 0x00003030,



	/* REO2TCL R0 ring configuration address */

	.hal_reo_tcl_ring_base_lsb = 0x000003fc,

	.hal_reo_tcl_ring_hp = 0x00003058,



	/* REO CMD ring address */

	.hal_reo_cmd_ring_base_lsb = 0x000000e4,

	.hal_reo_cmd_ring_hp = 0x00003010,



	/* REO status address */

	.hal_reo_status_ring_base_lsb = 0x00000504,

	.hal_reo_status_hp = 0x00003070,



	/* SW2REO ring address */

	.hal_sw2reo_ring_base_lsb = 0x0000013c,

	.hal_sw2reo_ring_hp = 0x00003018,



	/* WCSS relative address */

	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,

	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,

	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,

	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,



	/* WBM Idle address */

	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,

	.hal_wbm_idle_link_ring_misc = 0x00000884,



	/* SW2WBM release address */

	.hal_wbm_release_ring_base_lsb = 0x000001ec,



	/* WBM2SW release address */

	.hal_wbm0_release_ring_base_lsb = 0x00000924,

	.hal_wbm1_release_ring_base_lsb = 0x0000097c,



	/* PCIe base address */

	.pcie_qserdes_sysclk_en_sel = 0x0,

	.pcie_pcs_osc_dtct_config_base = 0x0,



	/* Shadow register area */

	.hal_shadow_base_addr = 0x00000504,

};



const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {

drivers/net/wireless/ath/ath11k/hw.h

+10 −0
Original line number Diff line number Diff line
@@ -253,6 +253,7 @@ extern const struct ath11k_hw_ops ipq6018_ops; 
extern const struct ath11k_hw_ops qca6390_ops;

extern const struct ath11k_hw_ops qcn9074_ops;

extern const struct ath11k_hw_ops wcn6855_ops;

extern const struct ath11k_hw_ops wcn6750_ops;



extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;

extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
@@ -355,6 +356,12 @@ struct ath11k_hw_regs { 
	u32 hal_reo_status_ring_base_lsb;

	u32 hal_reo_status_hp;



	u32 hal_reo_cmd_ring_base_lsb;

	u32 hal_reo_cmd_ring_hp;



	u32 hal_sw2reo_ring_base_lsb;

	u32 hal_sw2reo_ring_hp;



	u32 hal_seq_wcss_umac_ce0_src_reg;

	u32 hal_seq_wcss_umac_ce0_dst_reg;

	u32 hal_seq_wcss_umac_ce1_src_reg;
@@ -370,12 +377,15 @@ struct ath11k_hw_regs { 


	u32 pcie_qserdes_sysclk_en_sel;

	u32 pcie_pcs_osc_dtct_config_base;



	u32 hal_shadow_base_addr;

};



extern const struct ath11k_hw_regs ipq8074_regs;

extern const struct ath11k_hw_regs qca6390_regs;

extern const struct ath11k_hw_regs qcn9074_regs;

extern const struct ath11k_hw_regs wcn6855_regs;

extern const struct ath11k_hw_regs wcn6750_regs;



static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)

{