Commit 494f6ed8 authored by liaoguojia's avatar liaoguojia Committed by Jiantao Xiao
Browse files

net: hns3: add support for FD counter 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9A3QT


CVE: NA

----------------------------------------------------------------------

FD counter is used to count the number of times that the Flow Table rule
is hit. It is helpful when user want to take the accurate statistics of
some rules.

Signed-off-by: default avatarliaoguojia <liaoguojia@huawei.com>
Reviewed-by: default avatarshenjian 00434615 <shenjian15@huawei.com>
Reviewed-by: default avatarlipeng 00277521 <lipeng321@huawei.com>
Reviewed-by: default avatarpublic TuringEE <turingee@huawei.com>
Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 7bf2d3ba

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+6 −4
Original line number Diff line number Diff line
@@ -733,11 +733,11 @@ struct hclge_fd_tcam_config_3_cmd { 


#define HCLGE_FD_AD_DROP_B		0

#define HCLGE_FD_AD_DIRECT_QID_B	1

#define HCLGE_FD_AD_QID_S		2

#define HCLGE_FD_AD_QID_M		GENMASK(11, 2)

#define HCLGE_FD_AD_QID_L_S		2

#define HCLGE_FD_AD_QID_L_M		GENMASK(11, 2)

#define HCLGE_FD_AD_USE_COUNTER_B	12

#define HCLGE_FD_AD_COUNTER_NUM_S	13

#define HCLGE_FD_AD_COUNTER_NUM_M	GENMASK(20, 13)

#define HCLGE_FD_AD_COUNTER_NUM_L_S	13

#define HCLGE_FD_AD_COUNTER_NUM_L_M	GENMASK(19, 13)

#define HCLGE_FD_AD_NXT_STEP_B		20

#define HCLGE_FD_AD_NXT_KEY_S		21

#define HCLGE_FD_AD_NXT_KEY_M		GENMASK(25, 21)
@@ -747,6 +747,8 @@ struct hclge_fd_tcam_config_3_cmd { 
#define HCLGE_FD_AD_TC_OVRD_B		16

#define HCLGE_FD_AD_TC_SIZE_S		17

#define HCLGE_FD_AD_TC_SIZE_M		GENMASK(20, 17)

#define HCLGE_FD_AD_QID_H_B		21

#define HCLGE_FD_AD_COUNTER_NUM_H_B	26



struct hclge_fd_ad_config_cmd {

	u8 stage;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+9 −4
Original line number Diff line number Diff line
@@ -5785,6 +5785,8 @@ static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 
static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,

			      struct hclge_fd_ad_data *action)

{

#define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2	128



	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);

	struct hclge_fd_ad_config_cmd *req;

	struct hclge_desc desc;
@@ -5811,14 +5813,17 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 
	hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,

		      action->forward_to_direct_queue);

	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,

	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,

			action->queue_id);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);

	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,

			HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);

	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_L_M,

			HCLGE_FD_AD_COUNTER_NUM_L_S, action->counter_id);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);

	hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,

			action->counter_id);

			action->next_input_key);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,

		      action->queue_id >= HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 ?

		      1 : 0);



	req->ad_data = cpu_to_le64(ad_data);

	ret = hclge_cmd_send(&hdev->hw, &desc, 1);