Commit 490dd880 authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
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ARM: imx5: introduce DT includes for clock provider 



Use clock defines in order to make devicetrees more
human readable.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent c2ddbdf1

Documentation/devicetree/bindings/clock/imx5-clock.txt

+3 −193
Original line number Diff line number Diff line
@@ -7,198 +7,8 @@ Required properties: 
- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX5

clocks and IDs.



	Clock			ID

	---------------------------

	dummy			0

	ckil			1

	osc			2

	ckih1			3

	ckih2			4

	ahb			5

	ipg			6

	axi_a			7

	axi_b			8

	uart_pred		9

	uart_root		10

	esdhc_a_pred		11

	esdhc_b_pred		12

	esdhc_c_s		13

	esdhc_d_s		14

	emi_sel			15

	emi_slow_podf		16

	nfc_podf		17

	ecspi_pred		18

	ecspi_podf		19

	usboh3_pred		20

	usboh3_podf		21

	usb_phy_pred		22

	usb_phy_podf		23

	cpu_podf		24

	di_pred			25

	tve_s			27

	uart1_ipg_gate		28

	uart1_per_gate		29

	uart2_ipg_gate		30

	uart2_per_gate		31

	uart3_ipg_gate		32

	uart3_per_gate		33

	i2c1_gate		34

	i2c2_gate		35

	gpt_ipg_gate		36

	pwm1_ipg_gate		37

	pwm1_hf_gate		38

	pwm2_ipg_gate		39

	pwm2_hf_gate		40

	gpt_hf_gate		41

	fec_gate		42

	usboh3_per_gate		43

	esdhc1_ipg_gate		44

	esdhc2_ipg_gate		45

	esdhc3_ipg_gate		46

	esdhc4_ipg_gate		47

	ssi1_ipg_gate		48

	ssi2_ipg_gate		49

	ssi3_ipg_gate		50

	ecspi1_ipg_gate		51

	ecspi1_per_gate		52

	ecspi2_ipg_gate		53

	ecspi2_per_gate		54

	cspi_ipg_gate		55

	sdma_gate		56

	emi_slow_gate		57

	ipu_s			58

	ipu_gate		59

	nfc_gate		60

	ipu_di1_gate		61

	vpu_s			62

	vpu_gate		63

	vpu_reference_gate	64

	uart4_ipg_gate		65

	uart4_per_gate		66

	uart5_ipg_gate		67

	uart5_per_gate		68

	tve_gate		69

	tve_pred		70

	esdhc1_per_gate		71

	esdhc2_per_gate		72

	esdhc3_per_gate		73

	esdhc4_per_gate		74

	usb_phy_gate		75

	hsi2c_gate		76

	mipi_hsc1_gate		77

	mipi_hsc2_gate		78

	mipi_esc_gate		79

	mipi_hsp_gate		80

	ldb_di1_div_3_5		81

	ldb_di1_div		82

	ldb_di0_div_3_5		83

	ldb_di0_div		84

	ldb_di1_gate		85

	can2_serial_gate	86

	can2_ipg_gate		87

	i2c3_gate		88

	lp_apm			89

	periph_apm		90

	main_bus		91

	ahb_max			92

	aips_tz1		93

	aips_tz2		94

	tmax1			95

	tmax2			96

	tmax3			97

	spba			98

	uart_sel		99

	esdhc_a_sel		100

	esdhc_b_sel		101

	esdhc_a_podf		102

	esdhc_b_podf		103

	ecspi_sel		104

	usboh3_sel		105

	usb_phy_sel		106

	iim_gate		107

	usboh3_gate		108

	emi_fast_gate		109

	ipu_di0_gate		110

	gpc_dvfs		111

	pll1_sw			112

	pll2_sw			113

	pll3_sw			114

	ipu_di0_sel		115

	ipu_di1_sel		116

	tve_ext_sel		117

	mx51_mipi		118

	pll4_sw			119

	ldb_di1_sel		120

	di_pll4_podf		121

	ldb_di0_sel		122

	ldb_di0_gate		123

	usb_phy1_gate		124

	usb_phy2_gate		125

	per_lp_apm		126

	per_pred1		127

	per_pred2		128

	per_podf		129

	per_root		130

	ssi_apm			131

	ssi1_root_sel		132

	ssi2_root_sel		133

	ssi3_root_sel		134

	ssi_ext1_sel		135

	ssi_ext2_sel		136

	ssi_ext1_com_sel	137

	ssi_ext2_com_sel	138

	ssi1_root_pred		139

	ssi1_root_podf		140

	ssi2_root_pred		141

	ssi2_root_podf		142

	ssi_ext1_pred		143

	ssi_ext1_podf		144

	ssi_ext2_pred		145

	ssi_ext2_podf		146

	ssi1_root_gate		147

	ssi2_root_gate		148

	ssi3_root_gate		149

	ssi_ext1_gate		150

	ssi_ext2_gate		151

	epit1_ipg_gate		152

	epit1_hf_gate		153

	epit2_ipg_gate		154

	epit2_hf_gate		155

	can_sel			156

	can1_serial_gate	157

	can1_ipg_gate		158

	owire_gate		159

	gpu3d_s			160

	gpu2d_s			161

	gpu3d_gate		162

	gpu2d_gate		163

	garb_gate		164

	cko1_sel		165

	cko1_podf		166

	cko1			167

	cko2_sel		168

	cko2_podf		169

	cko2			170

	srtc_gate		171

	pata_gate		172

	sata_gate		173

	spdif_xtal_sel		174

	spdif0_sel		175

	spdif1_sel		176

	spdif0_pred		177

	spdif0_podf		178

	spdif1_pred		179

	spdif1_podf		180

	spdif0_com_sel		181

	spdif1_com_sel		182

	spdif0_gate		183

	spdif1_gate		184

	spdif_ipg_gate		185

	ocram			186

	sahara_ipg_gate		187

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h

for the full list of i.MX5 clock IDs.



Examples (for mx53):
@@ -213,7 +23,7 @@ can1: can@53fc8000 { 
	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";

	reg = <0x53fc8000 0x4000>;

	interrupts = <82>;

	clocks = <&clks 158>, <&clks 157>;

	clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;

	clock-names = "ipg", "per";

	status = "disabled";

};

arch/arm/mach-imx/clk-imx51-imx53.c

+372 −414

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/imx5-clock.h

0 → 100644
+202 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */



#ifndef __DT_BINDINGS_CLOCK_IMX5_H

#define __DT_BINDINGS_CLOCK_IMX5_H



#define IMX5_CLK_DUMMY			0

#define IMX5_CLK_CKIL			1

#define IMX5_CLK_OSC			2

#define IMX5_CLK_CKIH1			3

#define IMX5_CLK_CKIH2			4

#define IMX5_CLK_AHB			5

#define IMX5_CLK_IPG			6

#define IMX5_CLK_AXI_A			7

#define IMX5_CLK_AXI_B			8

#define IMX5_CLK_UART_PRED		9

#define IMX5_CLK_UART_ROOT		10

#define IMX5_CLK_ESDHC_A_PRED		11

#define IMX5_CLK_ESDHC_B_PRED		12

#define IMX5_CLK_ESDHC_C_SEL		13

#define IMX5_CLK_ESDHC_D_SEL		14

#define IMX5_CLK_EMI_SEL		15

#define IMX5_CLK_EMI_SLOW_PODF		16

#define IMX5_CLK_NFC_PODF		17

#define IMX5_CLK_ECSPI_PRED		18

#define IMX5_CLK_ECSPI_PODF		19

#define IMX5_CLK_USBOH3_PRED		20

#define IMX5_CLK_USBOH3_PODF		21

#define IMX5_CLK_USB_PHY_PRED		22

#define IMX5_CLK_USB_PHY_PODF		23

#define IMX5_CLK_CPU_PODF		24

#define IMX5_CLK_DI_PRED		25

#define IMX5_CLK_TVE_SEL		27

#define IMX5_CLK_UART1_IPG_GATE		28

#define IMX5_CLK_UART1_PER_GATE		29

#define IMX5_CLK_UART2_IPG_GATE		30

#define IMX5_CLK_UART2_PER_GATE		31

#define IMX5_CLK_UART3_IPG_GATE		32

#define IMX5_CLK_UART3_PER_GATE		33

#define IMX5_CLK_I2C1_GATE		34

#define IMX5_CLK_I2C2_GATE		35

#define IMX5_CLK_GPT_IPG_GATE		36

#define IMX5_CLK_PWM1_IPG_GATE		37

#define IMX5_CLK_PWM1_HF_GATE		38

#define IMX5_CLK_PWM2_IPG_GATE		39

#define IMX5_CLK_PWM2_HF_GATE		40

#define IMX5_CLK_GPT_HF_GATE		41

#define IMX5_CLK_FEC_GATE		42

#define IMX5_CLK_USBOH3_PER_GATE	43

#define IMX5_CLK_ESDHC1_IPG_GATE	44

#define IMX5_CLK_ESDHC2_IPG_GATE	45

#define IMX5_CLK_ESDHC3_IPG_GATE	46

#define IMX5_CLK_ESDHC4_IPG_GATE	47

#define IMX5_CLK_SSI1_IPG_GATE		48

#define IMX5_CLK_SSI2_IPG_GATE		49

#define IMX5_CLK_SSI3_IPG_GATE		50

#define IMX5_CLK_ECSPI1_IPG_GATE	51

#define IMX5_CLK_ECSPI1_PER_GATE	52

#define IMX5_CLK_ECSPI2_IPG_GATE	53

#define IMX5_CLK_ECSPI2_PER_GATE	54

#define IMX5_CLK_CSPI_IPG_GATE		55

#define IMX5_CLK_SDMA_GATE		56

#define IMX5_CLK_EMI_SLOW_GATE		57

#define IMX5_CLK_IPU_SEL		58

#define IMX5_CLK_IPU_GATE		59

#define IMX5_CLK_NFC_GATE		60

#define IMX5_CLK_IPU_DI1_GATE		61

#define IMX5_CLK_VPU_SEL		62

#define IMX5_CLK_VPU_GATE		63

#define IMX5_CLK_VPU_REFERENCE_GATE	64

#define IMX5_CLK_UART4_IPG_GATE		65

#define IMX5_CLK_UART4_PER_GATE		66

#define IMX5_CLK_UART5_IPG_GATE		67

#define IMX5_CLK_UART5_PER_GATE		68

#define IMX5_CLK_TVE_GATE		69

#define IMX5_CLK_TVE_PRED		70

#define IMX5_CLK_ESDHC1_PER_GATE	71

#define IMX5_CLK_ESDHC2_PER_GATE	72

#define IMX5_CLK_ESDHC3_PER_GATE	73

#define IMX5_CLK_ESDHC4_PER_GATE	74

#define IMX5_CLK_USB_PHY_GATE		75

#define IMX5_CLK_HSI2C_GATE		76

#define IMX5_CLK_MIPI_HSC1_GATE		77

#define IMX5_CLK_MIPI_HSC2_GATE		78

#define IMX5_CLK_MIPI_ESC_GATE		79

#define IMX5_CLK_MIPI_HSP_GATE		80

#define IMX5_CLK_LDB_DI1_DIV_3_5	81

#define IMX5_CLK_LDB_DI1_DIV		82

#define IMX5_CLK_LDB_DI0_DIV_3_5	83

#define IMX5_CLK_LDB_DI0_DIV		84

#define IMX5_CLK_LDB_DI1_GATE		85

#define IMX5_CLK_CAN2_SERIAL_GATE	86

#define IMX5_CLK_CAN2_IPG_GATE		87

#define IMX5_CLK_I2C3_GATE		88

#define IMX5_CLK_LP_APM			89

#define IMX5_CLK_PERIPH_APM		90

#define IMX5_CLK_MAIN_BUS		91

#define IMX5_CLK_AHB_MAX		92

#define IMX5_CLK_AIPS_TZ1		93

#define IMX5_CLK_AIPS_TZ2		94

#define IMX5_CLK_TMAX1			95

#define IMX5_CLK_TMAX2			96

#define IMX5_CLK_TMAX3			97

#define IMX5_CLK_SPBA			98

#define IMX5_CLK_UART_SEL		99

#define IMX5_CLK_ESDHC_A_SEL		100

#define IMX5_CLK_ESDHC_B_SEL		101

#define IMX5_CLK_ESDHC_A_PODF		102

#define IMX5_CLK_ESDHC_B_PODF		103

#define IMX5_CLK_ECSPI_SEL		104

#define IMX5_CLK_USBOH3_SEL		105

#define IMX5_CLK_USB_PHY_SEL		106

#define IMX5_CLK_IIM_GATE		107

#define IMX5_CLK_USBOH3_GATE		108

#define IMX5_CLK_EMI_FAST_GATE		109

#define IMX5_CLK_IPU_DI0_GATE		110

#define IMX5_CLK_GPC_DVFS		111

#define IMX5_CLK_PLL1_SW		112

#define IMX5_CLK_PLL2_SW		113

#define IMX5_CLK_PLL3_SW		114

#define IMX5_CLK_IPU_DI0_SEL		115

#define IMX5_CLK_IPU_DI1_SEL		116

#define IMX5_CLK_TVE_EXT_SEL		117

#define IMX5_CLK_MX51_MIPI		118

#define IMX5_CLK_PLL4_SW		119

#define IMX5_CLK_LDB_DI1_SEL		120

#define IMX5_CLK_DI_PLL4_PODF		121

#define IMX5_CLK_LDB_DI0_SEL		122

#define IMX5_CLK_LDB_DI0_GATE		123

#define IMX5_CLK_USB_PHY1_GATE		124

#define IMX5_CLK_USB_PHY2_GATE		125

#define IMX5_CLK_PER_LP_APM		126

#define IMX5_CLK_PER_PRED1		127

#define IMX5_CLK_PER_PRED2		128

#define IMX5_CLK_PER_PODF		129

#define IMX5_CLK_PER_ROOT		130

#define IMX5_CLK_SSI_APM		131

#define IMX5_CLK_SSI1_ROOT_SEL		132

#define IMX5_CLK_SSI2_ROOT_SEL		133

#define IMX5_CLK_SSI3_ROOT_SEL		134

#define IMX5_CLK_SSI_EXT1_SEL		135

#define IMX5_CLK_SSI_EXT2_SEL		136

#define IMX5_CLK_SSI_EXT1_COM_SEL	137

#define IMX5_CLK_SSI_EXT2_COM_SEL	138

#define IMX5_CLK_SSI1_ROOT_PRED		139

#define IMX5_CLK_SSI1_ROOT_PODF		140

#define IMX5_CLK_SSI2_ROOT_PRED		141

#define IMX5_CLK_SSI2_ROOT_PODF		142

#define IMX5_CLK_SSI_EXT1_PRED		143

#define IMX5_CLK_SSI_EXT1_PODF		144

#define IMX5_CLK_SSI_EXT2_PRED		145

#define IMX5_CLK_SSI_EXT2_PODF		146

#define IMX5_CLK_SSI1_ROOT_GATE		147

#define IMX5_CLK_SSI2_ROOT_GATE		148

#define IMX5_CLK_SSI3_ROOT_GATE		149

#define IMX5_CLK_SSI_EXT1_GATE		150

#define IMX5_CLK_SSI_EXT2_GATE		151

#define IMX5_CLK_EPIT1_IPG_GATE		152

#define IMX5_CLK_EPIT1_HF_GATE		153

#define IMX5_CLK_EPIT2_IPG_GATE		154

#define IMX5_CLK_EPIT2_HF_GATE		155

#define IMX5_CLK_CAN_SEL		156

#define IMX5_CLK_CAN1_SERIAL_GATE	157

#define IMX5_CLK_CAN1_IPG_GATE		158

#define IMX5_CLK_OWIRE_GATE		159

#define IMX5_CLK_GPU3D_SEL		160

#define IMX5_CLK_GPU2D_SEL		161

#define IMX5_CLK_GPU3D_GATE		162

#define IMX5_CLK_GPU2D_GATE		163

#define IMX5_CLK_GARB_GATE		164

#define IMX5_CLK_CKO1_SEL		165

#define IMX5_CLK_CKO1_PODF		166

#define IMX5_CLK_CKO1			167

#define IMX5_CLK_CKO2_SEL		168

#define IMX5_CLK_CKO2_PODF		169

#define IMX5_CLK_CKO2			170

#define IMX5_CLK_SRTC_GATE		171

#define IMX5_CLK_PATA_GATE		172

#define IMX5_CLK_SATA_GATE		173

#define IMX5_CLK_SPDIF_XTAL_SEL		174

#define IMX5_CLK_SPDIF0_SEL		175

#define IMX5_CLK_SPDIF1_SEL		176

#define IMX5_CLK_SPDIF0_PRED		177

#define IMX5_CLK_SPDIF0_PODF		178

#define IMX5_CLK_SPDIF1_PRED		179

#define IMX5_CLK_SPDIF1_PODF		180

#define IMX5_CLK_SPDIF0_COM_SEL		181

#define IMX5_CLK_SPDIF1_COM_SEL		182

#define IMX5_CLK_SPDIF0_GATE		183

#define IMX5_CLK_SPDIF1_GATE		184

#define IMX5_CLK_SPDIF_IPG_GATE		185

#define IMX5_CLK_OCRAM			186

#define IMX5_CLK_SAHARA_IPG_GATE	187

#define IMX5_CLK_END			188



#endif /* __DT_BINDINGS_CLOCK_IMX5_H */