Commit 48e07c23 authored by Christian König's avatar Christian König
Browse files

drm/ttm: nuke memory type flags 



It's not supported to specify more than one of those flags.
So it never made sense to make this a flag in the first place.

Nuke the flags and specify directly which memory type to use.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/389826/?series=81551&rev=1
parent e03d342c

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+15 −9
Original line number Diff line number Diff line
@@ -136,8 +136,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 


		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |

			TTM_PL_FLAG_VRAM;

		places[c].mem_type = TTM_PL_VRAM;

		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;



		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)

			places[c].lpfn = visible_pfn;
@@ -152,7 +152,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
	if (domain & AMDGPU_GEM_DOMAIN_GTT) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_TT;

		places[c].mem_type = TTM_PL_TT;

		places[c].flags = 0;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;
@@ -164,7 +165,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
	if (domain & AMDGPU_GEM_DOMAIN_CPU) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_SYSTEM;

		places[c].mem_type = TTM_PL_SYSTEM;

		places[c].flags = 0;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;
@@ -176,28 +178,32 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
	if (domain & AMDGPU_GEM_DOMAIN_GDS) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;

		places[c].mem_type = AMDGPU_PL_GDS;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_GWS) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;

		places[c].mem_type = AMDGPU_PL_GWS;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_OA) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;

		places[c].mem_type = AMDGPU_PL_OA;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		c++;

	}



	if (!c) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;

		places[c].mem_type = TTM_PL_SYSTEM;

		places[c].flags = TTM_PL_MASK_CACHING;

		c++;

	}
@@ -591,7 +597,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, 
		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);



	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&

	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {

	    bo->tbo.mem.mem_type == TTM_PL_VRAM) {

		struct dma_fence *fence;



		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+8 −5
Original line number Diff line number Diff line
@@ -88,7 +88,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 
	static const struct ttm_place placements = {

		.fpfn = 0,

		.lpfn = 0,

		.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM

		.mem_type = TTM_PL_SYSTEM,

		.flags = TTM_PL_MASK_CACHING

	};



	/* Don't handle scatter gather BOs */
@@ -533,7 +534,8 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 
	placement.busy_placement = &placements;

	placements.fpfn = 0;

	placements.lpfn = 0;

	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;

	placements.mem_type = TTM_PL_TT;

	placements.flags = TTM_PL_MASK_CACHING;

	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);

	if (unlikely(r)) {

		pr_err("Failed to find GTT space for blit from VRAM\n");
@@ -589,7 +591,8 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 
	placement.busy_placement = &placements;

	placements.fpfn = 0;

	placements.lpfn = 0;

	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;

	placements.mem_type = TTM_PL_TT;

	placements.flags = TTM_PL_MASK_CACHING;

	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);

	if (unlikely(r)) {

		pr_err("Failed to find GTT space for blit to VRAM\n");
@@ -1171,8 +1174,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 
		placement.busy_placement = &placements;

		placements.fpfn = 0;

		placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;

		placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |

			TTM_PL_FLAG_TT;

		placements.mem_type = TTM_PL_TT;

		placements.flags = bo->mem.placement;



		r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);

		if (unlikely(r))

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+0 −4
Original line number Diff line number Diff line
@@ -32,10 +32,6 @@ 
#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)

#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)



#define AMDGPU_PL_FLAG_GDS		(TTM_PL_FLAG_PRIV << 0)

#define AMDGPU_PL_FLAG_GWS		(TTM_PL_FLAG_PRIV << 1)

#define AMDGPU_PL_FLAG_OA		(TTM_PL_FLAG_PRIV << 2)



#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512

#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2

drivers/gpu/drm/drm_gem_vram_helper.c

+6 −9
Original line number Diff line number Diff line
@@ -145,21 +145,18 @@ static void drm_gem_vram_placement(struct drm_gem_vram_object *gbo, 
	gbo->placement.placement = gbo->placements;

	gbo->placement.busy_placement = gbo->placements;



	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM)

	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) {

		gbo->placements[c].mem_type = TTM_PL_VRAM;

		gbo->placements[c++].flags = TTM_PL_FLAG_WC |

					     TTM_PL_FLAG_UNCACHED |

					     TTM_PL_FLAG_VRAM |

					     invariant_flags;



	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM)

		gbo->placements[c++].flags = TTM_PL_MASK_CACHING |

					     TTM_PL_FLAG_SYSTEM |

					     invariant_flags;

	}



	if (!c)

	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM || !c) {

		gbo->placements[c].mem_type = TTM_PL_SYSTEM;

		gbo->placements[c++].flags = TTM_PL_MASK_CACHING |

					     TTM_PL_FLAG_SYSTEM |

					     invariant_flags;

	}



	gbo->placement.num_placement = c;

	gbo->placement.num_busy_placement = c;

drivers/gpu/drm/nouveau/nouveau_bo.c

+16 −8
Original line number Diff line number Diff line
@@ -345,12 +345,18 @@ set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain, 
{

	*n = 0;



	if (domain & NOUVEAU_GEM_DOMAIN_VRAM)

		pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;

	if (domain & NOUVEAU_GEM_DOMAIN_GART)

		pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;

	if (domain & NOUVEAU_GEM_DOMAIN_CPU)

		pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;

	if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {

		pl[*n].mem_type = TTM_PL_VRAM;

		pl[(*n)++].flags = flags;

	}

	if (domain & NOUVEAU_GEM_DOMAIN_GART) {

		pl[*n].mem_type = TTM_PL_TT;

		pl[(*n)++].flags = flags;

	}

	if (domain & NOUVEAU_GEM_DOMAIN_CPU) {

		pl[*n].mem_type = TTM_PL_SYSTEM;

		pl[(*n)++].flags = flags;

	}

}



static void
@@ -882,7 +888,8 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 
	struct ttm_place placement_memtype = {

		.fpfn = 0,

		.lpfn = 0,

		.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING

		.mem_type = TTM_PL_TT,

		.flags = TTM_PL_MASK_CACHING

	};

	struct ttm_placement placement;

	struct ttm_resource tmp_reg;
@@ -919,7 +926,8 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 
	struct ttm_place placement_memtype = {

		.fpfn = 0,

		.lpfn = 0,

		.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING

		.mem_type = TTM_PL_TT,

		.flags = TTM_PL_MASK_CACHING

	};

	struct ttm_placement placement;

	struct ttm_resource tmp_reg;