Commit 48d7927b authored by Paul Brook's avatar Paul Brook Committed by Catalin Marinas
Browse files

Add a prefetch abort handler 



This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: default avatarPaul Brook <paul@codesourcery.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent d7f864be

arch/arm/kernel/asm-offsets.c

+7 −0
Original line number Diff line number Diff line
@@ -111,5 +111,12 @@ int main(void) 
  DEFINE(PROCINFO_INITFUNC,	offsetof(struct proc_info_list, __cpu_flush));

  DEFINE(PROCINFO_MM_MMUFLAGS,	offsetof(struct proc_info_list, __cpu_mm_mmu_flags));

  DEFINE(PROCINFO_IO_MMUFLAGS,	offsetof(struct proc_info_list, __cpu_io_mmu_flags));

  BLANK();

#ifdef MULTI_DABORT

  DEFINE(PROCESSOR_DABT_FUNC,	offsetof(struct processor, _data_abort));

#endif

#ifdef MULTI_PABORT

  DEFINE(PROCESSOR_PABT_FUNC,	offsetof(struct processor, _prefetch_abort));

#endif

  return 0; 

}

arch/arm/kernel/entry-armv.S

+24 −10
Original line number Diff line number Diff line
@@ -166,12 +166,12 @@ __dabt_svc: 
	@ The abort handler must return the aborted address in r0, and

	@ the fault status register in r1.  r9 must be preserved.

	@

#ifdef MULTI_ABORT

#ifdef MULTI_DABORT

	ldr	r4, .LCprocfns

	mov	lr, pc

	ldr	pc, [r4]

	ldr	pc, [r4, #PROCESSOR_DABT_FUNC]

#else

	bl	CPU_ABORT_HANDLER

	bl	CPU_DABORT_HANDLER

#endif



	@
@@ -293,7 +293,6 @@ __pabt_svc: 
	mrs	r9, cpsr

	tst	r3, #PSR_I_BIT

	biceq	r9, r9, #PSR_I_BIT

	msr	cpsr_c, r9



	@

	@ set args, then call main handler
@@ -301,7 +300,15 @@ __pabt_svc: 
	@  r0 - address of faulting instruction

	@  r1 - pointer to registers on stack

	@

	mov	r0, r2				@ address (pc)

#ifdef MULTI_PABORT

	mov	r0, r2			@ pass address of aborted instruction.

	ldr	r4, .LCprocfns

	mov	lr, pc

	ldr	pc, [r4, #PROCESSOR_PABT_FUNC]

#else

	CPU_PABORT_HANDLER(r0, r2)

#endif

	msr	cpsr_c, r9			@ Maybe enable interrupts

	mov	r1, sp				@ regs

	bl	do_PrefetchAbort		@ call abort handler
@@ -320,7 +327,7 @@ __pabt_svc: 
	.align	5

.LCcralign:

	.word	cr_alignment

#ifdef MULTI_ABORT

#ifdef MULTI_DABORT

.LCprocfns:

	.word	processor

#endif
@@ -404,12 +411,12 @@ __dabt_usr: 
	@ The abort handler must return the aborted address in r0, and

	@ the fault status register in r1.

	@

#ifdef MULTI_ABORT

#ifdef MULTI_DABORT

	ldr	r4, .LCprocfns

	mov	lr, pc

	ldr	pc, [r4]

	ldr	pc, [r4, #PROCESSOR_DABT_FUNC]

#else

	bl	CPU_ABORT_HANDLER

	bl	CPU_DABORT_HANDLER

#endif



	@
@@ -619,8 +626,15 @@ __und_usr_unknown: 
__pabt_usr:

	usr_entry



#ifdef MULTI_PABORT

	mov	r0, r2			@ pass address of aborted instruction.

	ldr	r4, .LCprocfns

	mov	lr, pc

	ldr	pc, [r4, #PROCESSOR_PABT_FUNC]

#else

	CPU_PABORT_HANDLER(r0, r2)

#endif

	enable_irq				@ Enable interrupts

	mov	r0, r2				@ address (pc)

	mov	r1, sp				@ regs

	bl	do_PrefetchAbort		@ call abort handler

	/* fall through */

arch/arm/kernel/entry-common.S

+5 −0
Original line number Diff line number Diff line
@@ -352,6 +352,11 @@ sys_mmap2: 
		b	do_mmap2

#endif



ENTRY(pabort_ifar)

		mrc	p15, 0, r0, cr6, cr0, 2

ENTRY(pabort_noifar)

		mov	pc, lr



#ifdef CONFIG_OABI_COMPAT



/*

arch/arm/mm/Kconfig

+23 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ config CPU_ARM610 
	select CPU_CP15_MMU

	select CPU_COPY_V3 if MMU

	select CPU_TLB_V3 if MMU

	select CPU_PABRT_NOIFAR

	help

	  The ARM610 is the successor to the ARM3 processor

	  and was produced by VLSI Technology Inc.
@@ -49,6 +50,7 @@ config CPU_ARM710 
	select CPU_CP15_MMU

	select CPU_COPY_V3 if MMU

	select CPU_TLB_V3 if MMU

	select CPU_PABRT_NOIFAR

	help

	  A 32-bit RISC microprocessor based on the ARM7 processor core

	  designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,6 +66,7 @@ config CPU_ARM720T 
	default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X

	select CPU_32v4T

	select CPU_ABRT_LV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -113,6 +116,7 @@ config CPU_ARM920T 
	default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200

	select CPU_32v4T

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -135,6 +139,7 @@ config CPU_ARM922T 
	default y if ARCH_LH7A40X || ARCH_KS8695

	select CPU_32v4T

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -155,6 +160,7 @@ config CPU_ARM925T 
 	default y if ARCH_OMAP15XX

	select CPU_32v4T

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -175,6 +181,7 @@ config CPU_ARM926T 
	default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI

	select CPU_32v5

	select CPU_ABRT_EV5TJ

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU
@@ -226,6 +233,7 @@ config CPU_ARM1020 
	depends on ARCH_INTEGRATOR

	select CPU_32v5

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -244,6 +252,7 @@ config CPU_ARM1020E 
	depends on ARCH_INTEGRATOR

	select CPU_32v5

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -257,6 +266,7 @@ config CPU_ARM1022 
	depends on ARCH_INTEGRATOR

	select CPU_32v5

	select CPU_ABRT_EV4T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU # can probably do better
@@ -275,6 +285,7 @@ config CPU_ARM1026 
	depends on ARCH_INTEGRATOR

	select CPU_32v5

	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,6 +304,7 @@ config CPU_SA110 
	select CPU_32v3 if ARCH_RPC

	select CPU_32v4 if !ARCH_RPC

	select CPU_ABRT_EV4

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WB

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -314,6 +326,7 @@ config CPU_SA1100 
	default y

	select CPU_32v4

	select CPU_ABRT_EV4

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V4WB

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU
@@ -326,6 +339,7 @@ config CPU_XSCALE 
	default y

	select CPU_32v5

	select CPU_ABRT_EV5T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_TLB_V4WBI if MMU
@@ -349,6 +363,7 @@ config CPU_FEROCEON 
	default y

	select CPU_32v5

	select CPU_ABRT_EV5T

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU
@@ -371,6 +386,7 @@ config CPU_V6 
	default y if ARCH_MSM7X00A

	select CPU_32v6

	select CPU_ABRT_EV6

	select CPU_PABRT_NOIFAR

	select CPU_CACHE_V6

	select CPU_CACHE_VIPT

	select CPU_CP15_MMU
@@ -397,6 +413,7 @@ config CPU_V7 
	select CPU_32v6K

	select CPU_32v7

	select CPU_ABRT_EV7

	select CPU_PABRT_IFAR

	select CPU_CACHE_V7

	select CPU_CACHE_VIPT

	select CPU_CP15_MMU
@@ -458,6 +475,12 @@ config CPU_ABRT_EV6 
config CPU_ABRT_EV7

	bool



config CPU_PABRT_IFAR

	bool



config CPU_PABRT_NOIFAR

	bool



# The cache model

config CPU_CACHE_V3

	bool

arch/arm/mm/proc-arm1020.S

+1 −0
Original line number Diff line number Diff line
@@ -478,6 +478,7 @@ arm1020_processor_functions: 
	.word	cpu_arm1020_dcache_clean_area

	.word	cpu_arm1020_switch_mm

	.word	cpu_arm1020_set_pte_ext

	.word	pabort_noifar

	.size	arm1020_processor_functions, . - arm1020_processor_functions



	.section ".rodata"