Commit 48d216e5 authored by Vlad Buslov's avatar Vlad Buslov Committed by Saeed Mahameed
Browse files

net/mlx5e: Refactor reg_c1 usage 



Following patch in series uses reg_c1 in eswitch code. To use reg_c1
helpers in both TC and eswitch code, refactor existing helpers according to
similar use case of reg_c0 and move the functionality into eswitch.h.
Calculate reg mappings length from new defines to ensure that they are
always in sync and only need to be changed in single place.

Signed-off-by: default avatarVlad Buslov <vladbu@nvidia.com>
Signed-off-by: default avatarDmytro Linkin <dlinkin@nvidia.com>
Reviewed-by: default avatarRoi Dayan <roid@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent a508728a

drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c

+2 −2
Original line number Diff line number Diff line
@@ -651,7 +651,7 @@ bool mlx5e_rep_tc_update_skb(struct mlx5_cqe64 *cqe, 


		tc_skb_ext->chain = chain;



		zone_restore_id = reg_c1 & ZONE_RESTORE_MAX;

		zone_restore_id = reg_c1 & ESW_ZONE_ID_MASK;



		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);

		uplink_priv = &uplink_rpriv->uplink_priv;
@@ -660,7 +660,7 @@ bool mlx5e_rep_tc_update_skb(struct mlx5_cqe64 *cqe, 
			return false;

	}



	tunnel_id = reg_c1 >> REG_MAPPING_SHIFT(TUNNEL_TO_REG);

	tunnel_id = reg_c1 >> ESW_TUN_OFFSET;

	return mlx5e_restore_tunnel(priv, skb, tc_priv, tunnel_id);

#endif /* CONFIG_NET_TC_SKB_EXT */

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h

+2 −4
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ struct mlx5_ct_attr { 
#define zone_restore_to_reg_ct {\

	.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,\

	.moffset = 0,\

	.mlen = 1,\

	.mlen = (ESW_ZONE_ID_BITS / 8),\

	.soffset = MLX5_BYTE_OFF(fte_match_param,\

				 misc_parameters_2.metadata_reg_c_1) + 3,\

}
@@ -81,14 +81,12 @@ struct mlx5_ct_attr { 
#define nic_zone_restore_to_reg_ct {\

	.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,\

	.moffset = 2,\

	.mlen = 1,\

	.mlen = (ESW_ZONE_ID_BITS / 8),\

}



#define REG_MAPPING_MLEN(reg) (mlx5e_tc_attr_to_reg_mappings[reg].mlen)

#define REG_MAPPING_MOFFSET(reg) (mlx5e_tc_attr_to_reg_mappings[reg].moffset)

#define REG_MAPPING_SHIFT(reg) (REG_MAPPING_MOFFSET(reg) * 8)

#define ZONE_RESTORE_BITS (REG_MAPPING_MLEN(ZONE_RESTORE_TO_REG) * 8)

#define ZONE_RESTORE_MAX GENMASK(ZONE_RESTORE_BITS - 1, 0)



#if IS_ENABLED(CONFIG_MLX5_TC_CT)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

+2 −2
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = { 
	[TUNNEL_TO_REG] = {

		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,

		.moffset = 1,

		.mlen = 3,

		.mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),

		.soffset = MLX5_BYTE_OFF(fte_match_param,

					 misc_parameters_2.metadata_reg_c_1),

	},
@@ -5649,7 +5649,7 @@ bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, 
		tc_skb_ext->chain = chain;



		zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &

				  ZONE_RESTORE_MAX;

			ESW_ZONE_ID_MASK;



		if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,

					      zone_restore_id))

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

+1 −1
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe) 


	reg_b = be32_to_cpu(cqe->ft_metadata);



	if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ZONE_RESTORE_BITS))

	if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))

		return false;



	chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;

include/linux/mlx5/eswitch.h

+19 −0
Original line number Diff line number Diff line
@@ -98,6 +98,25 @@ u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, 
					      u16 vport_num);

u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,

					    u16 vport_num);



/* Reg C1 usage:

 * Reg C1 = < ESW_TUN_ID(12) | ESW_TUN_OPTS(12) | ESW_ZONE_ID(8) >

 *

 * Highest 12 bits of reg c1 is the encapsulation tunnel id, next 12 bits is

 * encapsulation tunnel options, and the lowest 8 bits are used for zone id.

 *

 * Zone id is used to restore CT flow when packet misses on chain.

 *

 * Tunnel id and options are used together to restore the tunnel info metadata

 * on miss and to support inner header rewrite by means of implicit chain 0

 * flows.

 */

#define ESW_ZONE_ID_BITS 8

#define ESW_TUN_OPTS_BITS 12

#define ESW_TUN_ID_BITS 12

#define ESW_TUN_OFFSET ESW_ZONE_ID_BITS

#define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)



u8 mlx5_eswitch_mode(struct mlx5_core_dev *dev);

#else  /* CONFIG_MLX5_ESWITCH */