Unverified Commit 48276242 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!11285 fix CVE-2024-43905

Merge Pull Request from: @ci-robot 
 
PR sync from: Liao Chen <liaochen4@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/WQAZGERXXAFMF5JHDZDP44OEIGT44CUU/ 
fix CVE-2024-43905

Bob Zhou (1):
  [Backport] drm/amd/pm: Fix the null pointer dereference for
    vega10_hwmgr


-- 
2.34.1
 
https://gitee.com/src-openeuler/kernel/issues/IAMMTH 
 
Link:https://gitee.com/openeuler/kernel/pulls/11285

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parents f63e9bf3 5865926d
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+26 −4
Original line number Diff line number Diff line
@@ -3388,13 +3388,17 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
	const struct vega10_power_state *vega10_ps =
			cast_const_phw_vega10_power_state(states->pnew_state);
	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
	uint32_t sclk = vega10_ps->performance_levels
			[vega10_ps->performance_level_count - 1].gfx_clock;
	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
	uint32_t mclk = vega10_ps->performance_levels
			[vega10_ps->performance_level_count - 1].mem_clock;
	uint32_t sclk, mclk;
	uint32_t i;

	if (vega10_ps == NULL)
		return -EINVAL;
	sclk = vega10_ps->performance_levels
			[vega10_ps->performance_level_count - 1].gfx_clock;
	mclk = vega10_ps->performance_levels
			[vega10_ps->performance_level_count - 1].mem_clock;

	for (i = 0; i < sclk_table->count; i++) {
		if (sclk == sclk_table->dpm_levels[i].value)
			break;
@@ -3701,6 +3705,9 @@ static int vega10_generate_dpm_level_enable_mask(
			cast_const_phw_vega10_power_state(states->pnew_state);
	int i;

	if (vega10_ps == NULL)
		return -EINVAL;

	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
			"Attempt to Trim DPM States Failed!",
			return -1);
@@ -4825,6 +4832,9 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,

	psa = cast_const_phw_vega10_power_state(pstate1);
	psb = cast_const_phw_vega10_power_state(pstate2);
	if (psa == NULL || psb == NULL)
		return -EINVAL;

	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
	if (psa->performance_level_count != psb->performance_level_count) {
		*equal = false;
@@ -4950,6 +4960,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
		return -EINVAL;

	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
	if (vega10_ps == NULL)
		return -EINVAL;

	vega10_ps->performance_levels
	[vega10_ps->performance_level_count - 1].gfx_clock =
@@ -5001,6 +5013,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
		return -EINVAL;

	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
	if (vega10_ps == NULL)
		return -EINVAL;

	vega10_ps->performance_levels
	[vega10_ps->performance_level_count - 1].mem_clock =
@@ -5236,6 +5250,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
		return;

	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
	if (vega10_ps == NULL)
		return;

	max_level = vega10_ps->performance_level_count - 1;

	if (vega10_ps->performance_levels[max_level].gfx_clock !=
@@ -5258,6 +5275,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)

	ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
	if (vega10_ps == NULL)
		return;

	max_level = vega10_ps->performance_level_count - 1;

	if (vega10_ps->performance_levels[max_level].gfx_clock !=
@@ -5448,6 +5468,8 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
		return -EINVAL;

	ps = cast_const_phw_vega10_power_state(state);
	if (ps == NULL)
		return -EINVAL;

	i = index > ps->performance_level_count - 1 ?
			ps->performance_level_count - 1 : index;