Commit 4817c37d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2021-12-23' of... 

Merge tag 'drm-intel-gt-next-2021-12-23' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

- Added bits of DG2 support around page table handling (Stuart Summers, Matthew Auld)
- Fixed wakeref leak in PMU busyness during reset in GuC mode (Umesh Nerlige Ramappa)
- Fixed debugfs access crash if GuC failed to load (John Harrison)
- Bring back GuC error log to error capture, undoing accidental earlier breakage (Thomas Hellström)
- Fixed memory leak in error capture caused by earlier refactoring (Thomas Hellström)
- Exclude reserved stolen from driver use (Chris Wilson)
- Add memory region sanity checking and optional full test (Chris Wilson)
- Fixed buffer size truncation in TTM shmemfs backend (Robert Beckett)
- Use correct lock and don't overwrite internal data structures when stealing GuC context ids (Matthew Brost)
- Don't hog IRQs when destroying GuC contexts (John Harrison)
- Make GuC to Host communication more robust (Matthew Brost)
- Continuation of locking refactoring around VMA and backing store handling (Maarten Lankhorst)
- Improve performance of reading GuC log from debugfs (John Harrison)
- Log when GuC fails to reset an engine (John Harrison)
- Speed up GuC/HuC firmware loading by requesting RP0 (Vinay Belgaumkar)
- Further work on asynchronous VMA unbinding (Thomas Hellström, Christian König)

- Refactor GuC/HuC firmware handling to prepare for future platforms (John Harrison)
- Prepare for future different GuC/HuC firmware signing key sizes (Daniele Ceraolo Spurio, Michal Wajdeczko)
- Add noreclaim annotations (Matthew Auld)
- Remove racey GEM_BUG_ON between GPU reset and GuC communication handling (Matthew Brost)
- Refactor i915->gt with to_gt(i915) to prepare for future platforms (Michał Winiarski, Andi Shyti)
- Increase GuC log size for CONFIG_DEBUG_GEM (John Harrison)

- Fixed engine busyness in selftests when in GuC mode (Umesh Nerlige Ramappa)
- Make engine parking work with PREEMPT_RT (Sebastian Andrzej Siewior)
- Replace X86_FEATURE_PAT with pat_enabled() (Lucas De Marchi)
- Selftest for stealing of guc ids (Matthew Brost)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YcRvKO5cyPvIxVCi@tursulin-mobl2
parents 78942ae4 6cb12fbd

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ i915-y += \ 
	  i915_active.o \

	  i915_buddy.o \

	  i915_cmd_parser.o \

	  i915_deps.o \

	  i915_gem_evict.o \

	  i915_gem_gtt.o \

	  i915_gem_ww.o \

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -819,7 +819,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, 
	 * maximum clocks following a vblank miss (see do_rps_boost()).

	 */

	if (!state->rps_interactive) {

		intel_rps_mark_interactive(&dev_priv->gt.rps, true);

		intel_rps_mark_interactive(&to_gt(dev_priv)->rps, true);

		state->rps_interactive = true;

	}
@@ -853,7 +853,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane, 
		return;



	if (state->rps_interactive) {

		intel_rps_mark_interactive(&dev_priv->gt.rps, false);

		intel_rps_mark_interactive(&to_gt(dev_priv)->rps, false);

		state->rps_interactive = false;

	}

drivers/gpu/drm/i915/display/intel_display.c

+9 −9
Original line number Diff line number Diff line
@@ -843,7 +843,7 @@ __intel_display_resume(struct drm_device *dev, 
static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)

{

	return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&

		intel_has_gpu_reset(&dev_priv->gt));

		intel_has_gpu_reset(to_gt(dev_priv)));

}



void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
@@ -862,14 +862,14 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 
		return;



	/* We have a modeset vs reset deadlock, defensively unbreak it. */

	set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);

	set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);

	smp_mb__after_atomic();

	wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);

	wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);



	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {

		drm_dbg_kms(&dev_priv->drm,

			    "Modeset potentially stuck, unbreaking through wedging\n");

		intel_gt_set_wedged(&dev_priv->gt);

		intel_gt_set_wedged(to_gt(dev_priv));

	}



	/*
@@ -920,7 +920,7 @@ void intel_display_finish_reset(struct drm_i915_private *dev_priv) 
		return;



	/* reset doesn't touch the display */

	if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))

	if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))

		return;



	state = fetch_and_zero(&dev_priv->modeset_restore_state);
@@ -958,7 +958,7 @@ void intel_display_finish_reset(struct drm_i915_private *dev_priv) 
	drm_modeset_acquire_fini(ctx);

	mutex_unlock(&dev->mode_config.mutex);



	clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);

	clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);

}



static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
@@ -8513,19 +8513,19 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat 
	for (;;) {

		prepare_to_wait(&intel_state->commit_ready.wait,

				&wait_fence, TASK_UNINTERRUPTIBLE);

		prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,

		prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,

					      I915_RESET_MODESET),

				&wait_reset, TASK_UNINTERRUPTIBLE);





		if (i915_sw_fence_done(&intel_state->commit_ready) ||

		    test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))

		    test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))

			break;



		schedule();

	}

	finish_wait(&intel_state->commit_ready.wait, &wait_fence);

	finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,

	finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,

				  I915_RESET_MODESET),

		    &wait_reset);

}

drivers/gpu/drm/i915/display/intel_dpt.c

+1 −3
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ intel_dpt_create(struct intel_framebuffer *fb) 


	vm = &dpt->vm;



	vm->gt = &i915->gt;

	vm->gt = to_gt(i915);

	vm->i915 = i915;

	vm->dma = i915->drm.dev;

	vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
@@ -279,8 +279,6 @@ intel_dpt_create(struct intel_framebuffer *fb) 


	vm->vma_ops.bind_vma    = dpt_bind_vma;

	vm->vma_ops.unbind_vma  = dpt_unbind_vma;

	vm->vma_ops.set_pages   = ggtt_set_pages;

	vm->vma_ops.clear_pages = clear_pages;



	vm->pte_encode = gen8_ggtt_pte_encode;

drivers/gpu/drm/i915/display/intel_overlay.c

+1 −1
Original line number Diff line number Diff line
@@ -1382,7 +1382,7 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv) 
	if (!HAS_OVERLAY(dev_priv))

		return;



	engine = dev_priv->gt.engine[RCS0];

	engine = to_gt(dev_priv)->engine[RCS0];

	if (!engine || !engine->kernel_context)

		return;