Commit 4812be97 authored by Dan Williams's avatar Dan Williams
Browse files

cxl/acpi: Introduce the root of a cxl_port topology 



While CXL builds upon the PCI software model for enumeration and
endpoint control, a static platform component is required to bootstrap
the CXL memory layout. Similar to how ACPI identifies root-level PCI
memory resources, ACPI data enumerates the address space and interleave
configuration for CXL Memory.

In addition to identifying host bridges, ACPI is responsible for
enumerating the CXL memory space that can be addressed by downstream
decoders. This is similar to the requirement for ACPI to publish
resources via the _CRS method for PCI host bridges. Specifically, ACPI
publishes a table, CXL Early Discovery Table (CEDT), which includes a
list of CXL Memory resources, CXL Fixed Memory Window Structures
(CFMWS).

For now, introduce the core infrastructure for a cxl_port hierarchy
starting with a root level anchor represented by the ACPI0017 device.

Follow on changes model support for the configurable decode capabilities
of cxl_port instances, i.e. CXL switch support.

Co-developed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Signed-off-by: default avatarAlison Schofield <alison.schofield@intel.com>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162325449515.2293126.15303270193010154608.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 54ada34b

Documentation/ABI/testing/sysfs-bus-cxl

+20 −0
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@@ -24,3 +24,23 @@ Description: 
		(RO) "Persistent Only Capacity" as bytes. Represents the

		identically named field in the Identify Memory Device Output

		Payload in the CXL-2.0 specification.



What:		/sys/bus/cxl/devices/*/devtype

Date:		June, 2021

KernelVersion:	v5.14

Contact:	linux-cxl@vger.kernel.org

Description:

		CXL device objects export the devtype attribute which mirrors

		the same value communicated in the DEVTYPE environment variable

		for uevents for devices on the "cxl" bus.



What:		/sys/bus/cxl/devices/portX/uport

Date:		June, 2021

KernelVersion:	v5.14

Contact:	linux-cxl@vger.kernel.org

Description:

		CXL port objects are enumerated from either a platform firmware

		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with

		CXL component registers. The 'uport' symlink connects the CXL

		portX object to the device that published the CXL port

		capability.

Documentation/driver-api/cxl/memory-devices.rst

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@@ -30,6 +30,12 @@ CXL Memory Device 


CXL Core

--------

.. kernel-doc:: drivers/cxl/cxl.h

   :doc: cxl objects



.. kernel-doc:: drivers/cxl/cxl.h

   :internal:



.. kernel-doc:: drivers/cxl/core.c

   :doc: cxl core

drivers/cxl/Kconfig

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@@ -45,4 +45,19 @@ config CXL_MEM_RAW_COMMANDS 
	  potential impact to memory currently in use by the kernel.



	  If developing CXL hardware or the driver say Y, otherwise say N.



config CXL_ACPI

	tristate "CXL ACPI: Platform Support"

	depends on ACPI

	help

	  Enable support for host managed device memory (HDM) resources

	  published by a platform's ACPI CXL memory layout description.  See

	  Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0

	  specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)

	  (https://www.computeexpresslink.org/spec-landing). The CXL core

	  consumes these resource to publish the root of a cxl_port decode

	  hierarchy to map regions that represent System RAM, or Persistent

	  Memory regions to be managed by LIBNVDIMM.



	  If unsure say 'm'.

endif

drivers/cxl/Makefile

+2 −0
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# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_CXL_BUS) += cxl_core.o

obj-$(CONFIG_CXL_MEM) += cxl_pci.o

obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o



ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL

cxl_core-y := core.o

cxl_pci-y := pci.o

cxl_acpi-y := acpi.o

drivers/cxl/acpi.c

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// SPDX-License-Identifier: GPL-2.0-only

/* Copyright(c) 2021 Intel Corporation. All rights reserved. */

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/device.h>

#include <linux/kernel.h>

#include <linux/acpi.h>

#include "cxl.h"



static int cxl_acpi_probe(struct platform_device *pdev)

{

	struct cxl_port *root_port;

	struct device *host = &pdev->dev;



	root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);

	if (IS_ERR(root_port))

		return PTR_ERR(root_port);

	dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));



	return 0;

}



static const struct acpi_device_id cxl_acpi_ids[] = {

	{ "ACPI0017", 0 },

	{ "", 0 },

};

MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);



static struct platform_driver cxl_acpi_driver = {

	.probe = cxl_acpi_probe,

	.driver = {

		.name = KBUILD_MODNAME,

		.acpi_match_table = cxl_acpi_ids,

	},

};



module_platform_driver(cxl_acpi_driver);

MODULE_LICENSE("GPL v2");

MODULE_IMPORT_NS(CXL);