Commit 47fabc9c authored Jun 07, 2019 by Clément Péron Committed by Mauro Carvalho Chehab Aug 04, 2019

media: dt-bindings: media: sunxi-ir: Add A31 compatible



Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
  and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sean Young <sean@mess.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>

parent b3185ab5

Documentation/devicetree/bindings/media/sunxi-ir.txt

+7 −2

Original line number	Diff line number	Diff line
		Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

		Required properties:
		- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
		- compatible :
		"allwinner,sun4i-a10-ir"
		"allwinner,sun5i-a13-ir"
		"allwinner,sun6i-a31-ir"
		- clocks : list of clock specifiers, corresponding to
		entries in clock-names property;
		- clock-names : should contain "apb" and "ir" entries;
		- interrupts : should contain IR IRQ number;
		- reg : should contain IO map address for IR.

		Required properties since A31:
		- resets : phandle + reset specifier pair

		Optional properties:
		- linux,rc-map-name: see rc.txt file in the same directory.
		- resets : phandle + reset specifier pair
		- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
		if missing.