Commit 47d8b302 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Andi Shyti
Browse files

drm/i915/mtl: Add workaround 14018778641 



WA 18018781329 is applicable now across all MTL
steppings.

V2:
  - Remove IS_MTL check, code already running for MTL - Matt

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230424101749.3719600-1-tejas.upadhyay@intel.com
parent e991b524

drivers/gpu/drm/i915/gt/intel_workarounds.c

+14 −16
Original line number Diff line number Diff line
@@ -1695,19 +1695,18 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
static void

xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)

{

	/* Wa_14018778641 / Wa_18018781329 */

	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);

	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);



	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {

		/* Wa_14014830051 */

		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);



		/* Wa_18018781329 */

		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);

		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);



		/* Wa_14015795083 */

		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);

	}



	/*

	 * Unlike older platforms, we no longer setup implicit steering here;

	 * all MCR accesses are explicitly steered.
@@ -1718,8 +1717,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
static void

xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)

{

	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {

	/*

	 * Wa_14018778641

	 * Wa_18018781329

	 *

	 * Note that although these registers are MCR on the primary
@@ -1728,7 +1727,6 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);

	wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);

	wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);

	}



	debug_dump_steering(gt);

}