Commit 47cfd061 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'pcs-xpcs-stmmac-add-1000BASE-X-AN-for-network-switch' 

Ong Boon Leong says:

====================
pcs-xpcs, stmmac: add 1000BASE-X AN for network switch

Thanks for v4 review feedback in [1] and [2]. I have changed the v5
implementation as follow.

v5 changes:
1/5 - No change from v4.
2/5 - No change from v4.
3/5 - [Fix] make xpcs_modify_changed() static and use
      mdiodev_modify_changed() for cleaner code as suggested by
      Russell King.
4/5 - [Fix] Use fwnode_get_phy_mode() as recommended by Andrew Lunn.
5/5 - [Fix] Make fwnode = of_fwnode_handle(priv->plat->phylink_node)
      order after priv = netdev_priv(dev).

v4 changes:
1/5 - Squash v3:1/7 & 2/7 patches into v4:1/6 so that it passes build.
2/5 - [No change] same as v3:3/7
3/5 - [Fix] Fix issues identified by Russell in [1]
4/5 - [Fix] Drop v3:5/7 patch per input by Russell in [2] and make
            dwmac-intel clear the ovr_an_inband flag if fixed-link
            is used in ACPI _DSD.
5/5 - [No change] same as v3:7/7

For the steps to setup ACPI _DSD and checking, they are the same
as in [3]

Reference:
[1] https://patchwork.kernel.org/comment/24894239/
[2] https://patchwork.kernel.org/comment/24895330/
[3] https://patchwork.kernel.org/project/netdevbpf/cover/20220610033610.114084-1-boon.leong.ong@intel.com/


====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 982c3e29 ab21cf92

drivers/net/dsa/sja1105/sja1105_main.c

+1 −1
Original line number Diff line number Diff line
@@ -2330,7 +2330,7 @@ int sja1105_static_config_reload(struct sja1105_private *priv, 
		else

			mode = MLO_AN_PHY;



		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);

		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode, NULL);

		if (rc < 0)

			goto out;

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+32 −2
Original line number Diff line number Diff line
@@ -251,7 +251,6 @@ static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) 
		priv->plat->mdio_bus_data->xpcs_an_inband = false;

	} else {

		priv->plat->max_speed = 1000;

		priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

		priv->plat->mdio_bus_data->xpcs_an_inband = true;

	}

}
@@ -443,6 +442,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat) 
static int intel_mgbe_common_data(struct pci_dev *pdev,

				  struct plat_stmmacenet_data *plat)

{

	struct fwnode_handle *fwnode;

	char clk_name[20];

	int ret;

	int i;
@@ -561,12 +561,42 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, 
	/* Use the last Rx queue */

	plat->vlan_fail_q = plat->rx_queues_to_use - 1;



	/* For fixed-link setup, we allow phy-mode setting */

	fwnode = dev_fwnode(&pdev->dev);

	if (fwnode) {

		int phy_mode;



		/* "phy-mode" setting is optional. If it is set,

		 *  we allow either sgmii or 1000base-x for now.

		 */

		phy_mode = fwnode_get_phy_mode(fwnode);

		if (phy_mode >= 0) {

			if (phy_mode == PHY_INTERFACE_MODE_SGMII ||

			    phy_mode == PHY_INTERFACE_MODE_1000BASEX)

				plat->phy_interface = phy_mode;

			else

				dev_warn(&pdev->dev, "Invalid phy-mode\n");

		}

	}



	/* Intel mgbe SGMII interface uses pcs-xcps */

	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) {

	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||

	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {

		plat->mdio_bus_data->has_xpcs = true;

		plat->mdio_bus_data->xpcs_an_inband = true;

	}



	/* For fixed-link setup, we clear xpcs_an_inband */

	if (fwnode) {

		struct fwnode_handle *fixed_node;



		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");

		if (fixed_node)

			plat->mdio_bus_data->xpcs_an_inband = false;



		fwnode_handle_put(fixed_node);

	}



	/* Ensure mdio bus scan skips intel serdes and pcs-xpcs */

	plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;

	plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

+7 −5
Original line number Diff line number Diff line
@@ -1128,18 +1128,20 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 
static int stmmac_init_phy(struct net_device *dev)

{

	struct stmmac_priv *priv = netdev_priv(dev);

	struct device_node *node;

	struct fwnode_handle *fwnode;

	int ret;



	node = priv->plat->phylink_node;

	fwnode = of_fwnode_handle(priv->plat->phylink_node);

	if (!fwnode)

		fwnode = dev_fwnode(priv->device);



	if (node)

		ret = phylink_of_phy_connect(priv->phylink, node, 0);

	if (fwnode)

		ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);



	/* Some DT bindings do not set-up the PHY handle. Let's try to

	 * manually parse it

	 */

	if (!node || ret) {

	if (!fwnode || ret) {

		int addr = priv->plat->phy_addr;

		struct phy_device *phydev;

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

+14 −0
Original line number Diff line number Diff line
@@ -434,9 +434,11 @@ int stmmac_mdio_register(struct net_device *ndev) 
	int err = 0;

	struct mii_bus *new_bus;

	struct stmmac_priv *priv = netdev_priv(ndev);

	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);

	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;

	struct device_node *mdio_node = priv->plat->mdio_node;

	struct device *dev = ndev->dev.parent;

	struct fwnode_handle *fixed_node;

	int addr, found, max_addr;



	if (!mdio_bus_data)
@@ -490,6 +492,18 @@ int stmmac_mdio_register(struct net_device *ndev) 
	if (priv->plat->has_xgmac)

		stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);



	/* If fixed-link is set, skip PHY scanning */

	if (!fwnode)

		fwnode = dev_fwnode(priv->device);



	if (fwnode) {

		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");

		if (fixed_node) {

			fwnode_handle_put(fixed_node);

			goto bus_register_done;

		}

	}



	if (priv->plat->phy_node || mdio_node)

		goto bus_register_done;

drivers/net/pcs/pcs-xpcs.c

+173 −3
Original line number Diff line number Diff line
@@ -77,6 +77,14 @@ static const int xpcs_sgmii_features[] = { 
	__ETHTOOL_LINK_MODE_MASK_NBITS,

};



static const int xpcs_1000basex_features[] = {

	ETHTOOL_LINK_MODE_Pause_BIT,

	ETHTOOL_LINK_MODE_Asym_Pause_BIT,

	ETHTOOL_LINK_MODE_Autoneg_BIT,

	ETHTOOL_LINK_MODE_1000baseX_Full_BIT,

	__ETHTOOL_LINK_MODE_MASK_NBITS,

};



static const int xpcs_2500basex_features[] = {

	ETHTOOL_LINK_MODE_Pause_BIT,

	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
@@ -102,6 +110,10 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = { 
	PHY_INTERFACE_MODE_SGMII,

};



static const phy_interface_t xpcs_1000basex_interfaces[] = {

	PHY_INTERFACE_MODE_1000BASEX,

};



static const phy_interface_t xpcs_2500basex_interfaces[] = {

	PHY_INTERFACE_MODE_2500BASEX,

	PHY_INTERFACE_MODE_MAX,
@@ -112,6 +124,7 @@ enum { 
	DW_XPCS_10GKR,

	DW_XPCS_XLGMII,

	DW_XPCS_SGMII,

	DW_XPCS_1000BASEX,

	DW_XPCS_2500BASEX,

	DW_XPCS_INTERFACE_MAX,

};
@@ -189,6 +202,14 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 
	return mdiobus_c45_write(bus, addr, dev, reg, val);

}



static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,

			       u16 mask, u16 set)

{

	u32 reg_addr = mdiobus_c45_addr(dev, reg);



	return mdiodev_modify_changed(xpcs->mdiodev, reg_addr, mask, set);

}



static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)

{

	return xpcs_read(xpcs, dev, DW_VENDOR | reg);
@@ -237,6 +258,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, 
		break;

	case DW_AN_C37_SGMII:

	case DW_2500BASEX:

	case DW_AN_C37_1000BASEX:

		dev = MDIO_MMD_VEND2;

		break;

	default:
@@ -772,6 +794,68 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode) 
	return ret;

}



static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, unsigned int mode,

					  const unsigned long *advertising)

{

	phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;

	int ret, mdio_ctrl, adv;

	bool changed = 0;



	/* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must

	 * be disabled first:-

	 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b

	 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)

	 */

	mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);

	if (mdio_ctrl < 0)

		return mdio_ctrl;



	if (mdio_ctrl & AN_CL37_EN) {

		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,

				 mdio_ctrl & ~AN_CL37_EN);

		if (ret < 0)

			return ret;

	}



	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);

	if (ret < 0)

		return ret;



	ret &= ~DW_VR_MII_PCS_MODE_MASK;

	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);

	if (ret < 0)

		return ret;



	/* Check for advertising changes and update the C45 MII ADV

	 * register accordingly.

	 */

	adv = phylink_mii_c22_pcs_encode_advertisement(interface,

						       advertising);

	if (adv >= 0) {

		ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,

					  MII_ADVERTISE, 0xffff, adv);

		if (ret < 0)

			return ret;



		changed = ret;

	}



	/* Clear CL37 AN complete status */

	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);

	if (ret < 0)

		return ret;



	if (phylink_autoneg_inband(mode) &&

	    linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {

		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,

				 mdio_ctrl | AN_CL37_EN);

		if (ret < 0)

			return ret;

	}



	return changed;

}



static int xpcs_config_2500basex(struct dw_xpcs *xpcs)

{

	int ret;
@@ -795,7 +879,7 @@ static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 
}



int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,

		   unsigned int mode)

		   unsigned int mode, const unsigned long *advertising)

{

	const struct xpcs_compat *compat;

	int ret;
@@ -817,6 +901,12 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 
		if (ret)

			return ret;

		break;

	case DW_AN_C37_1000BASEX:

		ret = xpcs_config_aneg_c37_1000basex(xpcs, mode,

						     advertising);

		if (ret)

			return ret;

		break;

	case DW_2500BASEX:

		ret = xpcs_config_2500basex(xpcs);

		if (ret)
@@ -843,7 +933,7 @@ static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode, 
{

	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);



	return xpcs_do_config(xpcs, interface, mode);

	return xpcs_do_config(xpcs, interface, mode, advertising);

}



static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
@@ -864,7 +954,7 @@ static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 


		state->link = 0;



		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND);

		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);

	}



	if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
@@ -921,6 +1011,29 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 
	return 0;

}



static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,

					struct phylink_link_state *state)

{

	int lpa, bmsr;



	if (state->an_enabled) {

		/* Reset link state */

		state->link = false;



		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);

		if (lpa < 0 || lpa & LPA_RFAULT)

			return lpa;



		bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);

		if (bmsr < 0)

			return bmsr;



		phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);

	}



	return 0;

}



static void xpcs_get_state(struct phylink_pcs *pcs,

			   struct phylink_link_state *state)

{
@@ -948,6 +1061,13 @@ static void xpcs_get_state(struct phylink_pcs *pcs, 
			       ERR_PTR(ret));

		}

		break;

	case DW_AN_C37_1000BASEX:

		ret = xpcs_get_state_c37_1000basex(xpcs, state);

		if (ret) {

			pr_err("xpcs_get_state_c37_1000basex returned %pe\n",

			       ERR_PTR(ret));

		}

		break;

	default:

		return;

	}
@@ -983,6 +1103,35 @@ static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode, 
		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));

}



static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int mode,

				   int speed, int duplex)

{

	int val, ret;



	if (phylink_autoneg_inband(mode))

		return;



	switch (speed) {

	case SPEED_1000:

		val = BMCR_SPEED1000;

		break;

	case SPEED_100:

	case SPEED_10:

	default:

		pr_err("%s: speed = %d\n", __func__, speed);

		return;

	}



	if (duplex == DUPLEX_FULL)

		val |= BMCR_FULLDPLX;

	else

		pr_err("%s: half duplex not supported\n", __func__);



	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);

	if (ret)

		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));

}



void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,

		  phy_interface_t interface, int speed, int duplex)

{
@@ -992,9 +1141,23 @@ void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 
		return xpcs_config_usxgmii(xpcs, speed);

	if (interface == PHY_INTERFACE_MODE_SGMII)

		return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);

	if (interface == PHY_INTERFACE_MODE_1000BASEX)

		return xpcs_link_up_1000basex(xpcs, mode, speed, duplex);

}

EXPORT_SYMBOL_GPL(xpcs_link_up);



static void xpcs_an_restart(struct phylink_pcs *pcs)

{

	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);

	int ret;



	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);

	if (ret >= 0) {

		ret |= BMCR_ANRESTART;

		xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);

	}

}



static u32 xpcs_get_id(struct dw_xpcs *xpcs)

{

	int ret;
@@ -1060,6 +1223,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { 
		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),

		.an_mode = DW_AN_C37_SGMII,

	},

	[DW_XPCS_1000BASEX] = {

		.supported = xpcs_1000basex_features,

		.interface = xpcs_1000basex_interfaces,

		.num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),

		.an_mode = DW_AN_C37_1000BASEX,

	},

	[DW_XPCS_2500BASEX] = {

		.supported = xpcs_2500basex_features,

		.interface = xpcs_2500basex_interfaces,
@@ -1115,6 +1284,7 @@ static const struct phylink_pcs_ops xpcs_phylink_ops = { 
	.pcs_validate = xpcs_validate,

	.pcs_config = xpcs_config,

	.pcs_get_state = xpcs_get_state,

	.pcs_an_restart = xpcs_an_restart,

	.pcs_link_up = xpcs_link_up,

};