Commit 479965a2 authored by Kristina Martsenko's avatar Kristina Martsenko Committed by Will Deacon
Browse files

arm64: cpufeature: Fix CLRBHB and BC detection 



ClearBHB support is indicated by the CLRBHB field in ID_AA64ISAR2_EL1.
Following some refactoring the kernel incorrectly checks the BC field
instead. Fix the detection to use the right field.

(Note: The original ClearBHB support had it as FTR_HIGHER_SAFE, but this
patch uses FTR_LOWER_SAFE, which seems more correct.)

Also fix the detection of BC (hinted conditional branches) to use
FTR_LOWER_SAFE, so that it is not reported on mismatched systems.

Fixes: 356137e6 ("arm64/sysreg: Make BHB clear feature defines match the architecture")
Fixes: 8fcc8285 ("arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230912133429.2606875-1-kristina.martsenko@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 215b215d

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -663,7 +663,7 @@ static inline bool supports_clearbhb(int scope) 
		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);



	return cpuid_feature_extract_unsigned_field(isar2,

						    ID_AA64ISAR2_EL1_BC_SHIFT);

						    ID_AA64ISAR2_EL1_CLRBHB_SHIFT);

}



const struct cpumask *system_32bit_el0_cpumask(void);

arch/arm64/kernel/cpufeature.c

+2 −1
Original line number Diff line number Diff line
@@ -222,7 +222,8 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),

arch/arm64/tools/sysreg

+5 −1
Original line number Diff line number Diff line
@@ -1347,7 +1347,11 @@ UnsignedEnum 51:48 RPRFM 
	0b0000	NI

	0b0001	IMP

EndEnum

Res0	47:28

Res0	47:32

UnsignedEnum	31:28	CLRBHB

	0b0000	NI

	0b0001	IMP

EndEnum

UnsignedEnum	27:24	PAC_frac

	0b0000	NI

	0b0001	IMP