Commit 4774faf8 authored by Frank Li's avatar Frank Li Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Implement generic suspend/resume functionality 

Introduce an helper function (dw_pcie_get_ltssm()) to retrieve
SMLH_LTSS_STATE.

Add common dw_pcie_suspend(resume)_noirq() API to implement the DWC
controller generic suspend/resume functionality.

Add a controller specific callback to send the PME_Turn_Off message
(ie .pme_turn_off) for controller platform specific PME handling.

Link: https://lore.kernel.org/r/20230821184815.2167131-3-Frank.Li@nxp.com


Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
[lpieralisi@kernel.org: commit log]
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: default avatarManivannan Sadhasivam <mani@kernel.org>
parent e78bd50b

drivers/pci/controller/dwc/pcie-designware-host.c

+71 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 * Author: Jingoo Han <jg1.han@samsung.com>

 */



#include <linux/iopoll.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/msi.h>
@@ -16,6 +17,7 @@ 
#include <linux/pci_regs.h>

#include <linux/platform_device.h>



#include "../../pci.h"

#include "pcie-designware.h"



static struct pci_ops dw_pcie_ops;
@@ -812,3 +814,72 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 
	return 0;

}

EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);



int dw_pcie_suspend_noirq(struct dw_pcie *pci)

{

	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	u32 val;

	int ret;



	/*

	 * If L1SS is supported, then do not put the link into L2 as some

	 * devices such as NVMe expect low resume latency.

	 */

	if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)

		return 0;



	if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)

		return 0;



	if (!pci->pp.ops->pme_turn_off)

		return 0;



	pci->pp.ops->pme_turn_off(&pci->pp);



	ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,

				PCIE_PME_TO_L2_TIMEOUT_US/10,

				PCIE_PME_TO_L2_TIMEOUT_US, false, pci);

	if (ret) {

		dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);

		return ret;

	}



	if (pci->pp.ops->host_deinit)

		pci->pp.ops->host_deinit(&pci->pp);



	pci->suspended = true;



	return ret;

}

EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);



int dw_pcie_resume_noirq(struct dw_pcie *pci)

{

	int ret;



	if (!pci->suspended)

		return 0;



	pci->suspended = false;



	if (pci->pp.ops->host_init) {

		ret = pci->pp.ops->host_init(&pci->pp);

		if (ret) {

			dev_err(pci->dev, "Host init failed: %d\n", ret);

			return ret;

		}

	}



	dw_pcie_setup_rc(&pci->pp);



	ret = dw_pcie_start_link(pci);

	if (ret)

		return ret;



	ret = dw_pcie_wait_for_link(pci);

	if (ret)

		return ret;



	return ret;

}

EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);

drivers/pci/controller/dwc/pcie-designware.h

+28 −0
Original line number Diff line number Diff line
@@ -288,10 +288,21 @@ enum dw_pcie_core_rst { 
	DW_PCIE_NUM_CORE_RSTS

};



enum dw_pcie_ltssm {

	/* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */

	DW_PCIE_LTSSM_DETECT_QUIET = 0x0,

	DW_PCIE_LTSSM_DETECT_ACT = 0x1,

	DW_PCIE_LTSSM_L0 = 0x11,

	DW_PCIE_LTSSM_L2_IDLE = 0x15,



	DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,

};



struct dw_pcie_host_ops {

	int (*host_init)(struct dw_pcie_rp *pp);

	void (*host_deinit)(struct dw_pcie_rp *pp);

	int (*msi_host_init)(struct dw_pcie_rp *pp);

	void (*pme_turn_off)(struct dw_pcie_rp *pp);

};



struct dw_pcie_rp {
@@ -364,6 +375,7 @@ struct dw_pcie_ops { 
	void    (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,

			      size_t size, u32 val);

	int	(*link_up)(struct dw_pcie *pcie);

	enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);

	int	(*start_link)(struct dw_pcie *pcie);

	void	(*stop_link)(struct dw_pcie *pcie);

};
@@ -393,6 +405,7 @@ struct dw_pcie { 
	struct reset_control_bulk_data	app_rsts[DW_PCIE_NUM_APP_RSTS];

	struct reset_control_bulk_data	core_rsts[DW_PCIE_NUM_CORE_RSTS];

	struct gpio_desc		*pe_rst;

	bool			suspended;

};



#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
@@ -431,6 +444,9 @@ int dw_pcie_edma_detect(struct dw_pcie *pci); 
void dw_pcie_edma_remove(struct dw_pcie *pci);

void dw_pcie_print_link_status(struct dw_pcie *pci);



int dw_pcie_suspend_noirq(struct dw_pcie *pci);

int dw_pcie_resume_noirq(struct dw_pcie *pci);



static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)

{

	dw_pcie_write_dbi(pci, reg, 0x4, val);
@@ -502,6 +518,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) 
		pci->ops->stop_link(pci);

}



static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)

{

	u32 val;



	if (pci->ops && pci->ops->get_ltssm)

		return pci->ops->get_ltssm(pci);



	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);



	return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);

}



#ifdef CONFIG_PCIE_DW_HOST

irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);

int dw_pcie_setup_rc(struct dw_pcie_rp *pp);