Commit 4772ade2 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/xilinx' 

- Add support for coherent PCIe DMA traffic using CCI (Bharat Kumar Gogada)

- Add optional "dma-coherent" DT property (Bharat Kumar Gogada)

* remotes/lorenzo/pci/xilinx:
  PCI: xilinx-nwl: Add optional "dma-coherent" property
  PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
parents 2a2dd35f 1c4422f2

Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ Required properties: 
	- #address-cells: specifies the number of cells needed to encode an

		address. The value must be 0.



Optional properties:

- dma-coherent: present if DMA operations are coherent



Example:

++++++++

drivers/pci/controller/pcie-xilinx-nwl.c

+7 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 


/* Bridge core config registers */

#define BRCFG_PCIE_RX0			0x00000000

#define BRCFG_PCIE_RX1			0x00000004

#define BRCFG_INTERRUPT			0x00000010

#define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
@@ -128,6 +129,7 @@ 
#define NWL_ECAM_VALUE_DEFAULT		12



#define CFG_DMA_REG_BAR			GENMASK(2, 0)

#define CFG_PCIE_CACHE			GENMASK(7, 0)



#define INT_PCI_MSI_NR			(2 * 32)
@@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 
	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,

			  BRCFG_PCIE_RX_MSG_FILTER);



	/* This routes the PCIe DMA traffic to go through CCI path */

	if (of_dma_is_coherent(dev->of_node))

		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |

				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);



	err = nwl_wait_for_link(pcie);

	if (err)

		return err;