Commit 476ac50f authored by Thong Thai's avatar Thong Thai Committed by Alex Deucher
Browse files

drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution 



Update the maximum resolution reported for HEVC encoding on VCN 3
devices to reflect its 8K encoding capability.

v2: Also update the max height for H.264 encoding to match spec.
(Ruijing)

Signed-off-by: default avatarThong Thai <thong.thai@amd.com>
Reviewed-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac9a7868

drivers/gpu/drm/amd/amdgpu/nv.c

+16 −6
Original line number Diff line number Diff line
@@ -98,6 +98,16 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = 
};



/* Sienna Cichlid */

static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},

};



static const struct amdgpu_video_codecs sc_video_codecs_encode = {

	.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),

	.codec_array = sc_video_codecs_encode_array,

};



static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =

{

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
@@ -136,8 +146,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 
/* SRIOV Sienna Cichlid, not const since data is controlled by host */

static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =

{

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},

};



static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
@@ -237,12 +247,12 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 
		} else {

			if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {

				if (encode)

					*codecs = &nv_video_codecs_encode;

					*codecs = &sc_video_codecs_encode;

				else

					*codecs = &sc_video_codecs_decode_vcn1;

			} else {

				if (encode)

					*codecs = &nv_video_codecs_encode;

					*codecs = &sc_video_codecs_encode;

				else

					*codecs = &sc_video_codecs_decode_vcn0;

			}
@@ -251,14 +261,14 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 
	case IP_VERSION(3, 0, 16):

	case IP_VERSION(3, 0, 2):

		if (encode)

			*codecs = &nv_video_codecs_encode;

			*codecs = &sc_video_codecs_encode;

		else

			*codecs = &sc_video_codecs_decode_vcn0;

		return 0;

	case IP_VERSION(3, 1, 1):

	case IP_VERSION(3, 1, 2):

		if (encode)

			*codecs = &nv_video_codecs_encode;

			*codecs = &sc_video_codecs_encode;

		else

			*codecs = &yc_video_codecs_decode;

		return 0;