Commit 4734a750 authored Mar 10, 2021 by Danielle Ratson Committed by David S. Miller Mar 10, 2021

mlxsw: Adjust some MFDE fields shift and size to fw implementation



MFDE.irisc_id and MFDE.event_id were adjusted according to what is
actually implemented in firmware.

Adjust the shift and size of these fields in mlxsw as well.

Note that the displacement of the first field is not a regression.
It was always incorrect and therefore reported "0".

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 315afd20

drivers/net/ethernet/mellanox/mlxsw/core.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1728,7 +1728,7 @@ static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *repor
		return err;

		event_id = mlxsw_reg_mfde_event_id_get(mfde_pl);
		err = devlink_fmsg_u8_pair_put(fmsg, "id", event_id);
		err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id);
		if (err)
		return err;
		switch (event_id) {

drivers/net/ethernet/mellanox/mlxsw/reg.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -10919,7 +10919,7 @@ MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
		* Which irisc triggered the event
		* Access: RO
		*/
		MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4);
		MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);

		enum mlxsw_reg_mfde_event_id {
		MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
		@@ -10930,7 +10930,7 @@ enum mlxsw_reg_mfde_event_id {
		/* reg_mfde_event_id
		* Access: RO
		*/
		MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8);
		MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);

		enum mlxsw_reg_mfde_method {
		MLXSW_REG_MFDE_METHOD_QUERY,