Commit 471c1dd9 authored by Reza Amini's avatar Reza Amini Committed by Alex Deucher
Browse files

drm/amd/display: Allow asic specific FSFT timing optimization 



[Why]
Each asic can optimize best based on its capabilities

[How]
Optimizing timing for a new pixel clock

Signed-off-by: default avatarReza Amini <Reza.Amini@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b6352dd

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+8 −10
Original line number Diff line number Diff line
@@ -246,20 +246,18 @@ struct dc_stream_status *dc_stream_get_status( 


#ifndef TRIM_FSFT

/**

 * dc_optimize_timing() - dc to optimize timing

 * dc_optimize_timing_for_fsft() - dc to optimize timing

 */

bool dc_optimize_timing(

	struct dc_crtc_timing *timing,

bool dc_optimize_timing_for_fsft(

	struct dc_stream_state *pStream,

	unsigned int max_input_rate_in_khz)

{

	//optimization is expected to assing a value to these:

	//timing->pix_clk_100hz

	//timing->v_front_porch

	//timing->v_total

	//timing->fast_transport_output_rate_100hz;

	timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;

	struct dc  *dc;



	return true;

	dc = pStream->ctx->dc;



	return (dc->hwss.optimize_timing_for_fsft &&

		dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));

}

#endif

drivers/gpu/drm/amd/display/dc/dc_stream.h

+2 −2
Original line number Diff line number Diff line
@@ -424,8 +424,8 @@ struct dc_stream_status *dc_stream_get_status( 
	struct dc_stream_state *dc_stream);



#ifndef TRIM_FSFT

bool dc_optimize_timing(

	struct dc_crtc_timing *timing,

bool dc_optimize_timing_for_fsft(

	struct dc_stream_state *pStream,

	unsigned int max_input_rate_in_khz);

#endif

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+27 −0
Original line number Diff line number Diff line
@@ -2498,3 +2498,30 @@ void dcn20_fpga_init_hw(struct dc *dc) 
		tg->funcs->tg_init(tg);

	}

}

#ifndef TRIM_FSFT

bool dcn20_optimize_timing_for_fsft(struct dc *dc,

		struct dc_crtc_timing *timing,

		unsigned int max_input_rate_in_khz)

{

	unsigned int old_v_front_porch;

	unsigned int old_v_total;

	unsigned int max_input_rate_in_100hz;

	unsigned long long new_v_total;



	max_input_rate_in_100hz = max_input_rate_in_khz * 10;

	if (max_input_rate_in_100hz < timing->pix_clk_100hz)

		return false;



	old_v_total = timing->v_total;

	old_v_front_porch = timing->v_front_porch;



	timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;

	timing->pix_clk_100hz = max_input_rate_in_100hz;



	new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);



	timing->v_total = new_v_total;

	timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);

	return true;

}

#endif

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

+5 −0
Original line number Diff line number Diff line
@@ -132,5 +132,10 @@ int dcn20_init_sys_ctx(struct dce_hwseq *hws, 
		struct dc *dc,

		struct dc_phy_addr_space_config *pa_config);



#ifndef TRIM_FSFT

bool dcn20_optimize_timing_for_fsft(struct dc *dc,

		struct dc_crtc_timing *timing,

		unsigned int max_input_rate_in_khz);

#endif

#endif /* __DC_HWSS_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

+3 −0
Original line number Diff line number Diff line
@@ -88,6 +88,9 @@ static const struct hw_sequencer_funcs dcn20_funcs = { 
	.set_backlight_level = dce110_set_backlight_level,

	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,

	.set_pipe = dce110_set_pipe,

#ifndef TRIM_FSFT

	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,

#endif

};



static const struct hwseq_private_funcs dcn20_private_funcs = {