Commit 46f9caf1 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Keep AMOR SPR a constant ~0 at runtime 



This register controls supervisor SPR modifications, and as such is only
relevant for KVM. KVM always sets AMOR to ~0 on guest entry, and never
restores it coming back out to the host, so it can be kept constant and
avoid the mtSPR in KVM guest entry.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Reviewed-by: default avatarFabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211123095231.1036501-10-npiggin@gmail.com
parent eacc8188

arch/powerpc/kernel/cpu_setup_power.c

+8 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ void __setup_cpu_power7(unsigned long offset, struct cpu_spec *t) 
		return;



	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);

}
@@ -150,6 +151,7 @@ void __restore_cpu_power7(void) 
		return;



	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);

}
@@ -164,6 +166,7 @@ void __setup_cpu_power8(unsigned long offset, struct cpu_spec *t) 
		return;



	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */

	init_HFSCR();
@@ -184,6 +187,7 @@ void __restore_cpu_power8(void) 
		return;



	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */

	init_HFSCR();
@@ -202,6 +206,7 @@ void __setup_cpu_power9(unsigned long offset, struct cpu_spec *t) 
	mtspr(SPRN_PSSCR, 0);

	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_PID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\

			 LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
@@ -223,6 +228,7 @@ void __restore_cpu_power9(void) 
	mtspr(SPRN_PSSCR, 0);

	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_PID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\

			 LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
@@ -242,6 +248,7 @@ void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t) 
	mtspr(SPRN_PSSCR, 0);

	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_PID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\

			 LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
@@ -264,6 +271,7 @@ void __restore_cpu_power10(void) 
	mtspr(SPRN_PSSCR, 0);

	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_PID, 0);

	mtspr(SPRN_AMOR, ~0);

	mtspr(SPRN_PCR, PCR_MASK);

	init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\

			 LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);

arch/powerpc/kernel/dt_cpu_ftrs.c

+2 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ static void __restore_cpu_cpufeatures(void) 
	mtspr(SPRN_LPCR, system_registers.lpcr);

	if (hv_mode) {

		mtspr(SPRN_LPID, 0);

		mtspr(SPRN_AMOR, ~0);

		mtspr(SPRN_HFSCR, system_registers.hfscr);

		mtspr(SPRN_PCR, system_registers.pcr);

	}
@@ -216,6 +217,7 @@ static int __init feat_enable_hv(struct dt_cpu_feature *f) 
	}



	mtspr(SPRN_LPID, 0);

	mtspr(SPRN_AMOR, ~0);



	lpcr = mfspr(SPRN_LPCR);

	lpcr &=  ~LPCR_LPES0; /* HV external interrupts */

arch/powerpc/kvm/book3s_hv_p9_entry.c

+0 −2
Original line number Diff line number Diff line
@@ -286,8 +286,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc 
	mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);

	mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);



	mtspr(SPRN_AMOR, ~0UL);



	local_paca->kvm_hstate.in_guest = KVM_GUEST_MODE_HV_P9;



	/*

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+0 −2
Original line number Diff line number Diff line
@@ -778,10 +778,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	/* Restore AMR and UAMOR, set AMOR to all 1s */

	ld	r5,VCPU_AMR(r4)

	ld	r6,VCPU_UAMOR(r4)

	li	r7,-1

	mtspr	SPRN_AMR,r5

	mtspr	SPRN_UAMOR,r6

	mtspr	SPRN_AMOR,r7



	/* Restore state of CTRL run bit; assume 1 on entry */

	lwz	r5,VCPU_CTRL(r4)

arch/powerpc/mm/book3s64/radix_pgtable.c

+0 −15
Original line number Diff line number Diff line
@@ -572,18 +572,6 @@ void __init radix__early_init_devtree(void) 
	return;

}



static void radix_init_amor(void)

{

	/*

	* In HV mode, we init AMOR (Authority Mask Override Register) so that

	* the hypervisor and guest can setup IAMR (Instruction Authority Mask

	* Register), enable key 0 and set it to 1.

	*

	* AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)

	*/

	mtspr(SPRN_AMOR, (3ul << 62));

}



void __init radix__early_init_mmu(void)

{

	unsigned long lpcr;
@@ -644,7 +632,6 @@ void __init radix__early_init_mmu(void) 
		lpcr = mfspr(SPRN_LPCR);

		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);

		radix_init_partition_table();

		radix_init_amor();

	} else {

		radix_init_pseries();

	}
@@ -668,8 +655,6 @@ void radix__early_init_mmu_secondary(void) 


		set_ptcr_when_no_uv(__pa(partition_tb) |

				    (PATB_SIZE_SHIFT - 12));



		radix_init_amor();

	}



	radix__switch_mmu_context(NULL, &init_mm);