Loading drivers/gpu/drm/radeon/evergreen_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -44,6 +44,9 @@ #define EVERGREEN_AUDIO_PLL1_DIV 0x5b4 #define EVERGREEN_AUDIO_PLL1_UNK 0x5bc #define EVERGREEN_CG_IND_ADDR 0x8f8 #define EVERGREEN_CG_IND_DATA 0x8fc #define EVERGREEN_AUDIO_ENABLE 0x5e78 #define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 Loading drivers/gpu/drm/radeon/radeon.h +17 −0 Original line number Diff line number Diff line Loading @@ -1852,6 +1852,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ Loading Loading @@ -1923,6 +1925,21 @@ static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(R600_RCU_DATA, (v)); } static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); r = RREG32(EVERGREEN_CG_IND_DATA); return r; } static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); WREG32(EVERGREEN_CG_IND_DATA, (v)); } void r100_pll_errata_after_index(struct radeon_device *rdev); Loading Loading
drivers/gpu/drm/radeon/evergreen_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -44,6 +44,9 @@ #define EVERGREEN_AUDIO_PLL1_DIV 0x5b4 #define EVERGREEN_AUDIO_PLL1_UNK 0x5bc #define EVERGREEN_CG_IND_ADDR 0x8f8 #define EVERGREEN_CG_IND_DATA 0x8fc #define EVERGREEN_AUDIO_ENABLE 0x5e78 #define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 Loading
drivers/gpu/drm/radeon/radeon.h +17 −0 Original line number Diff line number Diff line Loading @@ -1852,6 +1852,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ Loading Loading @@ -1923,6 +1925,21 @@ static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(R600_RCU_DATA, (v)); } static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); r = RREG32(EVERGREEN_CG_IND_DATA); return r; } static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); WREG32(EVERGREEN_CG_IND_DATA, (v)); } void r100_pll_errata_after_index(struct radeon_device *rdev); Loading