Commit 46f87632 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "There's the usual summary below, but the highlights are support for
  the Armv8.6 timer extensions, KASAN support for asymmetric MTE, the
  ability to kexec() with the MMU enabled and a second attempt at
  switching to the generic pfn_valid() implementation.

  Summary:

   - Support for the Arm8.6 timer extensions, including a
     self-synchronising view of the system registers to elide some
     expensive ISB instructions.

   - Exception table cleanup and rework so that the fixup handlers
     appear correctly in backtraces.

   - A handful of miscellaneous changes, the main one being selection of
     CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK.

   - More mm and pgtable cleanups.

   - KASAN support for "asymmetric" MTE, where tag faults are reported
     synchronously for loads (via an exception) and asynchronously for
     stores (via a register).

   - Support for leaving the MMU enabled during kexec relocation, which
     significantly speeds up the operation.

   - Minor improvements to our perf PMU drivers.

   - Improvements to the compat vDSO build system, particularly when
     building with LLVM=1.

   - Preparatory work for handling some Coresight TRBE tracing errata.

   - Cleanup and refactoring of the SVE code to pave the way for SME
     support in future.

   - Ensure SCS pages are unpoisoned immediately prior to freeing them
     when KASAN is enabled for the vmalloc area.

   - Try moving to the generic pfn_valid() implementation again now that
     the DMA mapping issue from last time has been resolved.

   - Numerous improvements and additions to our FPSIMD and SVE
     selftests"

[ armv8.6 timer updates were in a shared branch and already came in
  through -tip in the timer pull  - Linus ]

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (85 commits)
  arm64: Select POSIX_CPU_TIMERS_TASK_WORK
  arm64: Document boot requirements for FEAT_SME_FA64
  arm64/sve: Fix warnings when SVE is disabled
  arm64/sve: Add stub for sve_max_virtualisable_vl()
  arm64: errata: Add detection for TRBE write to out-of-range
  arm64: errata: Add workaround for TSB flush failures
  arm64: errata: Add detection for TRBE overwrite in FILL mode
  arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
  selftests: arm64: Factor out utility functions for assembly FP tests
  arm64: vmlinux.lds.S: remove `.fixup` section
  arm64: extable: add load_unaligned_zeropad() handler
  arm64: extable: add a dedicated uaccess handler
  arm64: extable: add `type` and `data` fields
  arm64: extable: use `ex` for `exception_table_entry`
  arm64: extable: make fixup_exception() return bool
  arm64: extable: consolidate definitions
  arm64: gpr-num: support W registers
  arm64: factor out GPR numbering helpers
  arm64: kvm: use kvm_exception_table_entry
  arm64: lib: __arch_copy_to_user(): fold fixups into body
  ...
parents 879dbe9f e6359798

Documentation/arm64/booting.rst

+10 −0
Original line number Diff line number Diff line
@@ -340,6 +340,16 @@ Before jumping into the kernel, the following conditions must be met: 
    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



  For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)



  - If EL3 is present:



    - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.



 - If the kernel is entered at EL1 and EL2 is present:



    - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented

Documentation/arm64/cpu-feature-registers.rst

+10 −2
Original line number Diff line number Diff line
@@ -235,7 +235,15 @@ infrastructure: 
     | DPB                          | [3-0]   |    y    |

     +------------------------------+---------+---------+



  6) ID_AA64MMFR2_EL1 - Memory model feature register 2

  6) ID_AA64MMFR0_EL1 - Memory model feature register 0



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | ECV                          | [63-60] |    y    |

     +------------------------------+---------+---------+



  7) ID_AA64MMFR2_EL1 - Memory model feature register 2



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |
@@ -243,7 +251,7 @@ infrastructure: 
     | AT                           | [35-32] |    y    |

     +------------------------------+---------+---------+



  7) ID_AA64ZFR0_EL1 - SVE feature ID register 0

  8) ID_AA64ZFR0_EL1 - SVE feature ID register 0



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

Documentation/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -247,6 +247,10 @@ HWCAP2_MTE 
    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described

    by Documentation/arm64/memory-tagging-extension.rst.



HWCAP2_ECV



    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

Documentation/arm64/silicon-errata.rst

+12 −0
Original line number Diff line number Diff line
@@ -92,12 +92,24 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

Documentation/dev-tools/kasan.rst

+5 −2
Original line number Diff line number Diff line
@@ -194,14 +194,17 @@ additional boot parameters that allow disabling KASAN or controlling features: 


- ``kasan=off`` or ``=on`` controls whether KASAN is enabled (default: ``on``).



- ``kasan.mode=sync`` or ``=async`` controls whether KASAN is configured in

  synchronous or asynchronous mode of execution (default: ``sync``).

- ``kasan.mode=sync``, ``=async`` or ``=asymm`` controls whether KASAN

  is configured in synchronous, asynchronous or asymmetric mode of

  execution (default: ``sync``).

  Synchronous mode: a bad access is detected immediately when a tag

  check fault occurs.

  Asynchronous mode: a bad access detection is delayed. When a tag check

  fault occurs, the information is stored in hardware (in the TFSR_EL1

  register for arm64). The kernel periodically checks the hardware and

  only reports tag faults during these checks.

  Asymmetric mode: a bad access is detected synchronously on reads and

  asynchronously on writes.



- ``kasan.stacktrace=off`` or ``=on`` disables or enables alloc and free stack

  traces collection (default: ``on``).