Commit 46dd40aa authored Oct 07, 2020 by Thomas Bogendoerfer

MIPS: SGI-IP28: disable use of ll/sc in kernel

SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock
up, if ll/sc sequences are issued in certain order. Since those systems
are all non-SMP, we can disable ll/sc usage in kernel.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent 43fab085

arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -25,7 +25,7 @@
		#define cpu_has_mcheck 0
		#define cpu_has_ejtag 0

		#define cpu_has_llsc 1
		#define cpu_has_llsc 0
		#define cpu_has_vtag_icache 0
		#define cpu_has_dc_aliases 0 /* see probe_pcache() */
		#define cpu_has_ic_fills_f_dc 0