Commit 46cf2c61 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:

 - Fix some register offsets on Intel Alderlake

 - Fix the order the UFS and SDC pins on Qualcomm SM6350

 - Fix a build error in Mediatek Moore.

 - Fix a pin function table in the Sunplus SP7021.

 - Fix some Kconfig and static keywords on the Samsung Tesla FSD SoC.

 - Fix up the EOI function for edge triggered IRQs and keep the block
   clock enabled for level IRQs in the STM32 driver.

 - Fix some bits and order in the Rockchip RK3308 driver.

 - Handle the errorpath in the Pistachio driver probe() properly.

* tag 'pinctrl-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: pistachio: fix use of irq_of_parse_and_map()
  pinctrl: stm32: Keep pinctrl block clock enabled when LEVEL IRQ requested
  pinctrl: rockchip: sort the rk3308_mux_recalced_data entries
  pinctrl: rockchip: fix RK3308 pinmux bits
  pinctrl: stm32: Do not call stm32_gpio_get() for edge triggered IRQs in EOI
  pinctrl: Fix an error in pin-function table of SP7021
  pinctrl: samsung: fix missing GPIOLIB on ARM64 Exynos config
  pinctrl: mediatek: moore: Fix build error
  pinctrl: qcom: sm6350: fix order of UFS & SDC pins
  pinctrl: alderlake: Fix register offsets for ADL-N variant
  pinctrl: samsung: staticize fsd_pin_ctrl
parents cf424ef0 0c9843a7

arch/arm/mach-exynos/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ menuconfig ARCH_EXYNOS 
	select EXYNOS_PMU

	select EXYNOS_SROM

	select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS

	select GPIOLIB

	select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5

	select HAVE_ARM_SCU if SMP

	select PINCTRL

drivers/pinctrl/intel/pinctrl-alderlake.c

+40 −20
Original line number Diff line number Diff line
@@ -14,11 +14,17 @@ 


#include "pinctrl-intel.h"



#define ADL_PAD_OWN	0x0a0

#define ADL_PADCFGLOCK	0x110

#define ADL_HOSTSW_OWN	0x150

#define ADL_GPI_IS	0x200

#define ADL_GPI_IE	0x220

#define ADL_N_PAD_OWN		0x020

#define ADL_N_PADCFGLOCK	0x080

#define ADL_N_HOSTSW_OWN	0x0b0

#define ADL_N_GPI_IS		0x100

#define ADL_N_GPI_IE		0x120



#define ADL_S_PAD_OWN		0x0a0

#define ADL_S_PADCFGLOCK	0x110

#define ADL_S_HOSTSW_OWN	0x150

#define ADL_S_GPI_IS		0x200

#define ADL_S_GPI_IE		0x220



#define ADL_GPP(r, s, e, g)				\

	{						\
@@ -28,14 +34,28 @@ 
		.gpio_base = (g),			\

	}



#define ADL_COMMUNITY(b, s, e, g)			\

#define ADL_N_COMMUNITY(b, s, e, g)			\

	{						\

		.barno = (b),				\

		.padown_offset = ADL_N_PAD_OWN,		\

		.padcfglock_offset = ADL_N_PADCFGLOCK,	\

		.hostown_offset = ADL_N_HOSTSW_OWN,	\

		.is_offset = ADL_N_GPI_IS,		\

		.ie_offset = ADL_N_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

		.gpps = (g),				\

		.ngpps = ARRAY_SIZE(g),			\

	}



#define ADL_S_COMMUNITY(b, s, e, g)			\

	{						\

		.barno = (b),				\

		.padown_offset = ADL_PAD_OWN,		\

		.padcfglock_offset = ADL_PADCFGLOCK,	\

		.hostown_offset = ADL_HOSTSW_OWN,	\

		.is_offset = ADL_GPI_IS,		\

		.ie_offset = ADL_GPI_IE,		\

		.padown_offset = ADL_S_PAD_OWN,		\

		.padcfglock_offset = ADL_S_PADCFGLOCK,	\

		.hostown_offset = ADL_S_HOSTSW_OWN,	\

		.is_offset = ADL_S_GPI_IS,		\

		.ie_offset = ADL_S_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

		.gpps = (g),				\
@@ -342,10 +362,10 @@ static const struct intel_padgroup adln_community5_gpps[] = { 
};



static const struct intel_community adln_communities[] = {

	ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),

	ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),

	ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),

	ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),

	ADL_N_COMMUNITY(0, 0, 66, adln_community0_gpps),

	ADL_N_COMMUNITY(1, 67, 168, adln_community1_gpps),

	ADL_N_COMMUNITY(2, 169, 248, adln_community4_gpps),

	ADL_N_COMMUNITY(3, 249, 256, adln_community5_gpps),

};



static const struct intel_pinctrl_soc_data adln_soc_data = {
@@ -713,11 +733,11 @@ static const struct intel_padgroup adls_community5_gpps[] = { 
};



static const struct intel_community adls_communities[] = {

	ADL_COMMUNITY(0, 0, 94, adls_community0_gpps),

	ADL_COMMUNITY(1, 95, 150, adls_community1_gpps),

	ADL_COMMUNITY(2, 151, 199, adls_community3_gpps),

	ADL_COMMUNITY(3, 200, 269, adls_community4_gpps),

	ADL_COMMUNITY(4, 270, 303, adls_community5_gpps),

	ADL_S_COMMUNITY(0, 0, 94, adls_community0_gpps),

	ADL_S_COMMUNITY(1, 95, 150, adls_community1_gpps),

	ADL_S_COMMUNITY(2, 151, 199, adls_community3_gpps),

	ADL_S_COMMUNITY(3, 200, 269, adls_community4_gpps),

	ADL_S_COMMUNITY(4, 270, 303, adls_community5_gpps),

};



static const struct intel_pinctrl_soc_data adls_soc_data = {

drivers/pinctrl/mediatek/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ config PINCTRL_MTK_MOORE 
	select GENERIC_PINMUX_FUNCTIONS

	select GPIOLIB

	select OF_GPIO

	select EINT_MTK

	select PINCTRL_MTK_V2



config PINCTRL_MTK_PARIS

drivers/pinctrl/pinctrl-pistachio.c

+3 −3
Original line number Diff line number Diff line
@@ -1374,10 +1374,10 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) 
		}



		irq = irq_of_parse_and_map(child, 0);

		if (irq < 0) {

			dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);

		if (!irq) {

			dev_err(pctl->dev, "No IRQ for bank %u\n", i);

			of_node_put(child);

			ret = irq;

			ret = -EINVAL;

			goto err;

		}

drivers/pinctrl/pinctrl-rockchip.c

+42 −27
Original line number Diff line number Diff line
@@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 


static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {

	{

		/* gpio1b6_sel */

		.num = 1,

		.pin = 14,

		.reg = 0x28,

		.bit = 12,

		.mask = 0xf

	}, {

		/* gpio1b7_sel */

		.num = 1,

		.pin = 15,

		.reg = 0x2c,

		.bit = 0,

		.mask = 0x3

	}, {

		/* gpio1c2_sel */

		.num = 1,

		.pin = 18,

		.reg = 0x30,

		.bit = 4,

		.mask = 0xf

	}, {

		/* gpio1c3_sel */

		.num = 1,

		.pin = 19,

		.reg = 0x30,

		.bit = 8,

		.mask = 0xf

	}, {

		/* gpio1c4_sel */

		.num = 1,

		.pin = 20,

		.reg = 0x30,

		.bit = 12,

		.mask = 0xf

	}, {

		/* gpio1c5_sel */

		.num = 1,

		.pin = 21,

		.reg = 0x34,

		.bit = 0,

		.mask = 0xf

	}, {

		/* gpio1c6_sel */

		.num = 1,

		.pin = 22,

		.reg = 0x34,

		.bit = 4,

		.mask = 0xf

	}, {

		/* gpio1c7_sel */

		.num = 1,

		.pin = 23,

		.reg = 0x34,

		.bit = 8,

		.mask = 0xf

	}, {

		.num = 3,

		.pin = 12,

		.reg = 0x68,

		.bit = 8,

		.mask = 0xf

	}, {

		.num = 3,

		.pin = 13,

		.reg = 0x68,

		.bit = 12,

		.mask = 0xf

	}, {

		/* gpio2a2_sel */

		.num = 2,

		.pin = 2,

		.reg = 0x608,

		.bit = 0,

		.mask = 0x7

		.reg = 0x40,

		.bit = 4,

		.mask = 0x3

	}, {

		/* gpio2a3_sel */

		.num = 2,

		.pin = 3,

		.reg = 0x608,

		.bit = 4,

		.mask = 0x7

		.reg = 0x40,

		.bit = 6,

		.mask = 0x3

	}, {

		/* gpio2c0_sel */

		.num = 2,

		.pin = 16,

		.reg = 0x610,

		.bit = 8,

		.mask = 0x7

		.reg = 0x50,

		.bit = 0,

		.mask = 0x3

	}, {

		/* gpio3b2_sel */

		.num = 3,

		.pin = 10,

		.reg = 0x610,

		.bit = 0,

		.mask = 0x7

		.reg = 0x68,

		.bit = 4,

		.mask = 0x3

	}, {

		/* gpio3b3_sel */

		.num = 3,

		.pin = 11,

		.reg = 0x610,

		.bit = 4,

		.mask = 0x7

		.reg = 0x68,

		.bit = 6,

		.mask = 0x3

	}, {

		/* gpio3b4_sel */

		.num = 3,

		.pin = 12,

		.reg = 0x68,

		.bit = 8,

		.mask = 0xf

	}, {

		/* gpio3b5_sel */

		.num = 3,

		.pin = 13,

		.reg = 0x68,

		.bit = 12,

		.mask = 0xf

	},

};