platform/x86/intel/ifs: Introduce Array Scan test to IFS

mainline inclusion
from mainline-v6.4-rc1
commit d31bbdf4
category: feature
feature: Backport Intel In Field Scan(IFS) Array BIST support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I73EG8
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/


commit/?id=d31bbdf4

Intel-SIG: commit d31bbdf4 ("platform/x86/intel/ifs: Introduce Array Scan test to IFS")

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platform/x86/intel/ifs: Introduce Array Scan test to IFS

Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.

Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).

Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.

Upcoming patches will add actual support.

Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20230322003359.213046-6-jithu.joseph@intel.com


Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>