Commit 46509e75 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.19' of... 

Merge tag 'phy-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-work-next

Vinod writes:

phy-for-5.19

  - New support:
        - LVDS configuration support and implementation in fsl driver
	- Qualcomm UFS phy support for SM6350 and USB PHY for SDX65
	- Allwinner D-PHY Rx mode support
	- Yamilfy Mixel mipi-dsi-phy

  - Updates:
	- Documentation for phy ops order
        - Can transceiver mux support
	- Qualcomm QMP phy updates
	- Uniphier phy updates

* tag 'phy-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits)
  phy: qcom-qmp: rename error labels
  phy: qcom-qmp: fix pipe-clock imbalance on power-on failure
  phy: qcom-qmp: switch to explicit reset helpers
  phy: qcom-qmp: fix reset-controller leak on probe errors
  phy: qcom-qmp: fix struct clk leak on probe errors
  dt-bindings: phy: renesas,usb2-phy: Document RZ/G2UL phy bindings
  dt-bindings: phy: marvell,armada-3700-utmi-host-phy: Fix incorrect compatible in example
  phy: qcom-qmp: fix phy-descriptor kernel-doc typo
  phy: rockchip-inno-usb2: Clean up some inconsistent indenting
  phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED
  phy: core: Warn when phy_power_on is called before phy_init
  phy: core: Update documentation syntax
  phy: core: Add documentation of phy operation order
  phy: rockchip-inno-usb2: Handle ID IRQ
  phy: rockchip-inno-usb2: Handle bvalid falling
  phy: rockchip-inno-usb2: Support multi-bit mask properties
  phy: rockchip-inno-usb2: Do not lock in bvalid IRQ handler
  phy: rockchip-inno-usb2: Do not check bvalid twice
  phy: rockchip-inno-usb2: Fix muxed interrupt support
  phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
  ...
parents 46ee6bca d413a349

Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

+12 −0
Original line number Diff line number Diff line
@@ -37,6 +37,18 @@ properties: 
  resets:

    maxItems: 1



  allwinner,direction:

    $ref: '/schemas/types.yaml#/definitions/string'

    description: |

      Direction of the D-PHY:

      - "rx" for receiving (e.g. when used with MIPI CSI-2);

      - "tx" for transmitting (e.g. when used with MIPI DSI).



    enum:

      - tx

      - rx

    default: tx



required:

  - "#phy-cells"

  - compatible

Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ additionalProperties: false 
examples:

  - |

    usb2_utmi_host_phy: phy@5f000 {

      compatible = "marvell,armada-3700-utmi-host-phy";

      compatible = "marvell,a3700-utmi-host-phy";

      reg = <0x5f000 0x800>;

      marvell,usb-misc-reg = <&usb2_syscon>;

      #phy-cells = <0>;

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt

deleted100644 → 0
+0 −29
Original line number Diff line number Diff line 
Mixel DSI PHY for i.MX8



The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

electrical signals for DSI.



Required properties:

- compatible: Must be:

  - "fsl,imx8mq-mipi-dphy"

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must contain the following entries:

  - "phy_ref": phandle and specifier referring to the DPHY ref clock

- reg: the register range of the PHY controller

- #phy-cells: number of cells in PHY, as defined in

  Documentation/devicetree/bindings/phy/phy-bindings.txt

  this must be <0>



Optional properties:

- power-domains: phandle to power domain



Example:

	dphy: dphy@30a0030 {

		compatible = "fsl,imx8mq-mipi-dphy";

		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

		clock-names = "phy_ref";

		reg = <0x30a00300 0x100>;

		power-domains = <&pd_mipi0>;

		#phy-cells = <0>;

        };

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml

0 → 100644
+107 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mixel DSI PHY for i.MX8



maintainers:

  - Guido Günther <agx@sigxcpu.org>



description: |

  The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

  electrical signals for DSI.



  The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work

  in either MIPI-DSI PHY mode or LVDS PHY mode.



properties:

  compatible:

    enum:

      - fsl,imx8mq-mipi-dphy

      - fsl,imx8qxp-mipi-dphy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: phy_ref



  assigned-clocks:

    maxItems: 1



  assigned-clock-parents:

    maxItems: 1



  assigned-clock-rates:

    maxItems: 1



  "#phy-cells":

    const: 0



  fsl,syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      A phandle which points to Control and Status Registers(CSR) module.



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#phy-cells"

  - power-domains



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8mq-mipi-dphy

    then:

      properties:

        fsl,syscon: false



      required:

        - assigned-clocks

        - assigned-clock-parents

        - assigned-clock-rates



  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qxp-mipi-dphy

    then:

      properties:

        assigned-clocks: false

        assigned-clock-parents: false

        assigned-clock-rates: false



      required:

        - fsl,syscon



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mq-clock.h>

    dphy: dphy@30a0030 {

        compatible = "fsl,imx8mq-mipi-dphy";

        reg = <0x30a00300 0x100>;

        clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

        clock-names = "phy_ref";

        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;

        assigned-clock-rates = <24000000>;

        #phy-cells = <0>;

        power-domains = <&pgc_mipi>;

    };

Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml

+4 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ properties: 
      - qcom,sdm845-qmp-usb3-phy

      - qcom,sdm845-qmp-usb3-uni-phy

      - qcom,sm6115-qmp-ufs-phy

      - qcom,sm6350-qmp-ufs-phy

      - qcom,sm8150-qmp-ufs-phy

      - qcom,sm8150-qmp-usb3-phy

      - qcom,sm8150-qmp-usb3-uni-phy
@@ -57,6 +58,7 @@ properties: 
      - qcom,sm8450-qmp-usb3-phy

      - qcom,sdx55-qmp-pcie-phy

      - qcom,sdx55-qmp-usb3-uni-phy

      - qcom,sdx65-qmp-usb3-uni-phy



  reg:

    minItems: 1
@@ -163,6 +165,7 @@ allOf: 
          contains:

            enum:

              - qcom,sdx55-qmp-usb3-uni-phy

              - qcom,sdx65-qmp-usb3-uni-phy

    then:

      properties:

        clocks:
@@ -279,6 +282,7 @@ allOf: 
            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sdm845-qmp-ufs-phy

              - qcom,sm6350-qmp-ufs-phy

              - qcom,sm8150-qmp-ufs-phy

              - qcom,sm8250-qmp-ufs-phy

              - qcom,sc8180x-qmp-ufs-phy