Commit 464f2164 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: Add missing ERX*_EL1 encodings 



We only describe a few of the ERX*_EL1 registers. Add the missing
ones (ERXPFGF_EL1, ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1 and
ERXMISC3_EL1).

Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Reviewed-by: default avatarMiguel Luis <miguel.luis@oracle.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarJing Zhang <jingzhangos@google.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230815183903.2735724-3-maz@kernel.org
parent 21f74a51

arch/arm64/include/asm/sysreg.h

+5 −0
Original line number Diff line number Diff line
@@ -229,8 +229,13 @@ 
#define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)

#define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)

#define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)

#define SYS_ERXPFGF_EL1			sys_reg(3, 0, 5, 4, 4)

#define SYS_ERXPFGCTL_EL1		sys_reg(3, 0, 5, 4, 5)

#define SYS_ERXPFGCDN_EL1		sys_reg(3, 0, 5, 4, 6)

#define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)

#define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)

#define SYS_ERXMISC2_EL1		sys_reg(3, 0, 5, 5, 2)

#define SYS_ERXMISC3_EL1		sys_reg(3, 0, 5, 5, 3)

#define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)

#define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)