Commit 464d2ff7 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v5.11-2' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/events updates from Daniel Lezcano:

 - Fix error handling if no clock is available on dw_apb_timer_of (Dinh Nguyen)

 - Fix overhead for erratum handling when the timer has no erratum and
   fix fault programing for the event stream on the arm arch timer
   (Keqian Zhu)

 - Fix potential deadlock when calling runtime PM on sh_cmt (Niklas
   Söderlund)
parents aa3b66f4 8ae954ca

drivers/clocksource/arm_arch_timer.c

+18 −9
Original line number Diff line number Diff line
@@ -396,10 +396,10 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long 
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;



	if (access == ARCH_TIMER_PHYS_ACCESS) {

		cval = evt + arch_counter_get_cntpct();

		cval = evt + arch_counter_get_cntpct_stable();

		write_sysreg(cval, cntp_cval_el0);

	} else {

		cval = evt + arch_counter_get_cntvct();

		cval = evt + arch_counter_get_cntvct_stable();

		write_sysreg(cval, cntv_cval_el0);

	}
@@ -822,15 +822,24 @@ static void arch_timer_evtstrm_enable(int divider) 


static void arch_timer_configure_evtstream(void)

{

	int evt_stream_div, pos;

	int evt_stream_div, lsb;



	/*

	 * As the event stream can at most be generated at half the frequency

	 * of the counter, use half the frequency when computing the divider.

	 */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;



	/*

	 * Find the closest power of two to the divisor. If the adjacent bit

	 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).

	 */

	lsb = fls(evt_stream_div) - 1;

	if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))

		lsb++;



	/* Find the closest power of two to the divisor */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;

	pos = fls(evt_stream_div);

	if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))

		pos--;

	/* enable event stream */

	arch_timer_evtstrm_enable(min(pos, 15));

	arch_timer_evtstrm_enable(max(0, min(lsb, 15)));

}



static void arch_counter_set_user_access(void)

drivers/clocksource/dw_apb_timer_of.c

+39 −18
Original line number Diff line number Diff line
@@ -14,12 +14,13 @@ 
#include <linux/reset.h>

#include <linux/sched_clock.h>



static void __init timer_get_base_and_rate(struct device_node *np,

static int __init timer_get_base_and_rate(struct device_node *np,

				    void __iomem **base, u32 *rate)

{

	struct clk *timer_clk;

	struct clk *pclk;

	struct reset_control *rstc;

	int ret;



	*base = of_iomap(np, 0);
@@ -46,55 +47,67 @@ static void __init timer_get_base_and_rate(struct device_node *np, 
			pr_warn("pclk for %pOFn is present, but could not be activated\n",

				np);



	if (!of_property_read_u32(np, "clock-freq", rate) &&

	    !of_property_read_u32(np, "clock-frequency", rate))

		return 0;



	timer_clk = of_clk_get_by_name(np, "timer");

	if (IS_ERR(timer_clk))

		goto try_clock_freq;

		return PTR_ERR(timer_clk);



	ret = clk_prepare_enable(timer_clk);

	if (ret)

		return ret;



	if (!clk_prepare_enable(timer_clk)) {

	*rate = clk_get_rate(timer_clk);

		return;

	}

	if (!(*rate))

		return -EINVAL;



try_clock_freq:

	if (of_property_read_u32(np, "clock-freq", rate) &&

	    of_property_read_u32(np, "clock-frequency", rate))

		panic("No clock nor clock-frequency property for %pOFn", np);

	return 0;

}



static void __init add_clockevent(struct device_node *event_timer)

static int __init add_clockevent(struct device_node *event_timer)

{

	void __iomem *iobase;

	struct dw_apb_clock_event_device *ced;

	u32 irq, rate;

	int ret = 0;



	irq = irq_of_parse_and_map(event_timer, 0);

	if (irq == 0)

		panic("No IRQ for clock event timer");



	timer_get_base_and_rate(event_timer, &iobase, &rate);

	ret = timer_get_base_and_rate(event_timer, &iobase, &rate);

	if (ret)

		return ret;



	ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,

				     rate);

	if (!ced)

		panic("Unable to initialise clockevent device");

		return -EINVAL;



	dw_apb_clockevent_register(ced);



	return 0;

}



static void __iomem *sched_io_base;

static u32 sched_rate;



static void __init add_clocksource(struct device_node *source_timer)

static int __init add_clocksource(struct device_node *source_timer)

{

	void __iomem *iobase;

	struct dw_apb_clocksource *cs;

	u32 rate;

	int ret;



	timer_get_base_and_rate(source_timer, &iobase, &rate);

	ret = timer_get_base_and_rate(source_timer, &iobase, &rate);

	if (ret)

		return ret;



	cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);

	if (!cs)

		panic("Unable to initialise clocksource device");

		return -EINVAL;



	dw_apb_clocksource_start(cs);

	dw_apb_clocksource_register(cs);
@@ -106,6 +119,8 @@ static void __init add_clocksource(struct device_node *source_timer) 
	 */

	sched_io_base = iobase + 0x04;

	sched_rate = rate;



	return 0;

}



static u64 notrace read_sched_clock(void)
@@ -146,10 +161,14 @@ static struct delay_timer dw_apb_delay_timer = { 
static int num_called;

static int __init dw_apb_timer_init(struct device_node *timer)

{

	int ret = 0;



	switch (num_called) {

	case 1:

		pr_debug("%s: found clocksource timer\n", __func__);

		add_clocksource(timer);

		ret = add_clocksource(timer);

		if (ret)

			return ret;

		init_sched_clock();

#ifdef CONFIG_ARM

		dw_apb_delay_timer.freq = sched_rate;
@@ -158,7 +177,9 @@ static int __init dw_apb_timer_init(struct device_node *timer) 
		break;

	default:

		pr_debug("%s: found clockevent timer\n", __func__);

		add_clockevent(timer);

		ret = add_clockevent(timer);

		if (ret)

			return ret;

		break;

	}

drivers/clocksource/sh_cmt.c

+14 −4
Original line number Diff line number Diff line
@@ -319,7 +319,6 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch) 
{

	int k, ret;



	pm_runtime_get_sync(&ch->cmt->pdev->dev);

	dev_pm_syscore_device(&ch->cmt->pdev->dev, true);



	/* enable clock */
@@ -394,7 +393,6 @@ static void sh_cmt_disable(struct sh_cmt_channel *ch) 
	clk_disable(ch->cmt->clk);



	dev_pm_syscore_device(&ch->cmt->pdev->dev, false);

	pm_runtime_put(&ch->cmt->pdev->dev);

}



/* private flags */
@@ -562,10 +560,16 @@ static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) 
	int ret = 0;

	unsigned long flags;



	if (flag & FLAG_CLOCKSOURCE)

		pm_runtime_get_sync(&ch->cmt->pdev->dev);



	raw_spin_lock_irqsave(&ch->lock, flags);



	if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))

	if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {

		if (flag & FLAG_CLOCKEVENT)

			pm_runtime_get_sync(&ch->cmt->pdev->dev);

		ret = sh_cmt_enable(ch);

	}



	if (ret)

		goto out;
@@ -590,14 +594,20 @@ static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) 
	f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);

	ch->flags &= ~flag;



	if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))

	if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {

		sh_cmt_disable(ch);

		if (flag & FLAG_CLOCKEVENT)

			pm_runtime_put(&ch->cmt->pdev->dev);

	}



	/* adjust the timeout to maximum if only clocksource left */

	if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))

		__sh_cmt_set_next(ch, ch->max_match_value);



	raw_spin_unlock_irqrestore(&ch->lock, flags);



	if (flag & FLAG_CLOCKSOURCE)

		pm_runtime_put(&ch->cmt->pdev->dev);

}



static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)