Unverified Commit 464b0187 authored Jul 22, 2022 by Atish Patra Committed by Palmer Dabbelt Aug 11, 2022

RISC-V: Enable sstc extension parsing from DT



The ISA extension framework now allows parsing any multi-letter
ISA extension.

Enable that for sstc extension.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220722165047.519994-3-atishp@rivosinc.com


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent bf952a29

arch/riscv/include/asm/hwcap.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -53,6 +53,7 @@ extern unsigned long elf_hwcap;
		enum riscv_isa_ext_id {
		RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
		RISCV_ISA_EXT_SVPBMT,
		RISCV_ISA_EXT_SSTC,
		RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
		};

arch/riscv/kernel/cpu.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node)
		static struct riscv_isa_ext_data isa_ext_arr[] = {
		__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
		__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
		__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
		__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
		};

arch/riscv/kernel/cpufeature.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void)
		} else {
		SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
		SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
		SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
		}
		#undef SET_ISA_EXT_MAP
		}