Commit 462c5c0a authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Rob Herring
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dt-bindings: ufs: qcom,ufs: convert to dtschema



Convert the Qualcomm Universal Flash Storage (UFS) Controller to DT
schema format.

Except the conversion, add also properties already present in DTS:
iommus, interconnects and power-domains.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220306111125.116455-6-krzysztof.kozlowski@canonical.com
parent 578f116b
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Universal Flash Storage (UFS) Controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Andy Gross <agross@kernel.org>

# Select only our matches, not all jedec,ufs-2.0
select:
  properties:
    compatible:
      contains:
        const: qcom,ufshc
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - qcom,msm8994-ufshc
          - qcom,msm8996-ufshc
          - qcom,msm8998-ufshc
          - qcom,sdm845-ufshc
          - qcom,sm8150-ufshc
          - qcom,sm8250-ufshc
          - qcom,sm8350-ufshc
          - qcom,sm8450-ufshc
      - const: qcom,ufshc
      - const: jedec,ufs-2.0

  clocks:
    minItems: 8
    maxItems: 11

  clock-names:
    minItems: 8
    maxItems: 11

  interconnects:
    minItems: 2
    maxItems: 2

  interconnect-names:
    items:
      - const: ufs-ddr
      - const: cpu-ufs

  iommus:
    minItems: 1
    maxItems: 2

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: ufsphy

  power-domains:
    maxItems: 1

  reg:
    minItems: 1
    maxItems: 2

  resets:
    maxItems: 1

  '#reset-cells':
    const: 1

  reset-names:
    items:
      - const: rst

  reset-gpios:
    maxItems: 1
    description:
      GPIO connected to the RESET pin of the UFS memory device.

required:
  - compatible
  - reg

allOf:
  - $ref: ufs-common.yaml

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-ufshc
              - qcom,sm8250-ufshc
              - qcom,sm8350-ufshc
              - qcom,sm8450-ufshc
    then:
      properties:
        clocks:
          minItems: 8
          maxItems: 8
        clock-names:
          items:
            - const: core_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
            - const: rx_lane1_sync_clk
        reg:
          minItems: 1
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-ufshc
              - qcom,sm8150-ufshc
    then:
      properties:
        clocks:
          minItems: 9
          maxItems: 9
        clock-names:
          items:
            - const: core_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
            - const: rx_lane1_sync_clk
            - const: ice_core_clk
        reg:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-ufshc
    then:
      properties:
        clocks:
          minItems: 11
          maxItems: 11
        clock-names:
          items:
            - const: core_clk_src
            - const: core_clk
            - const: bus_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro_src
            - const: core_clk_unipro
            - const: core_clk_ice
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
        reg:
          minItems: 1
          maxItems: 1

    # TODO: define clock bindings for qcom,msm8994-ufshc

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interconnect/qcom,sm8450.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs@1d84000 {
            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
                         "jedec,ufs-2.0";
            reg = <0 0x01d84000 0 0x3000>;
            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
            phys = <&ufs_mem_phy_lanes>;
            phy-names = "ufsphy";
            lanes-per-direction = <2>;
            #reset-cells = <1>;
            resets = <&gcc GCC_UFS_PHY_BCR>;
            reset-names = "rst";
            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;

            vcc-supply = <&vreg_l7b_2p5>;
            vcc-max-microamp = <1100000>;
            vccq-supply = <&vreg_l9b_1p2>;
            vccq-max-microamp = <1200000>;

            power-domains = <&gcc UFS_PHY_GDSC>;
            iommus = <&apps_smmu 0xe0 0x0>;
            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
            interconnect-names = "ufs-ddr", "cpu-ufs";

            clock-names = "core_clk",
                          "bus_aggr_clk",
                          "iface_clk",
                          "core_clk_unipro",
                          "ref_clk",
                          "tx_lane0_sync_clk",
                          "rx_lane0_sync_clk",
                          "rx_lane1_sync_clk";
            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
                     <&gcc GCC_UFS_PHY_AHB_CLK>,
                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>,
                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
            freq-table-hz = <75000000 300000000>,
                            <0 0>,
                            <0 0>,
                            <75000000 300000000>,
                            <75000000 300000000>,
                            <0 0>,
                            <0 0>,
                            <0 0>;
        };
    };
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* Universal Flash Storage (UFS) Host Controller

UFSHC nodes are defined to describe on-chip UFS host controllers.
Each UFS controller instance should have its own node.

Required properties:
- compatible		: must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"

			  For Qualcomm SoCs must contain, as below, an
			  SoC-specific compatible along with "qcom,ufshc" and
			  the appropriate jedec string:
			    "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
			    "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- interrupts        : <interrupt mapping for UFS host controller IRQ>
- reg               : <registers mapping>

Optional properties:
- phys                  : phandle to UFS PHY node
- phy-names             : the string "ufsphy" when is found in a node, along
                          with "phys" attribute, provides phandle to UFS PHY node
- vdd-hba-supply        : phandle to UFS host controller supply regulator node
- vcc-supply            : phandle to VCC supply regulator node
- vccq-supply           : phandle to VCCQ supply regulator node
- vccq2-supply          : phandle to VCCQ2 supply regulator node
- vcc-supply-1p8        : For embedded UFS devices, valid VCC range is 1.7-1.95V
                          or 2.7-3.6V. This boolean property when set, specifies
			  to use low voltage range of 1.7-1.95V. Note for external
			  UFS cards this property is invalid and valid VCC range is
			  always 2.7-3.6V.
- vcc-max-microamp      : specifies max. load that can be drawn from vcc supply
- vccq-max-microamp     : specifies max. load that can be drawn from vccq supply
- vccq2-max-microamp    : specifies max. load that can be drawn from vccq2 supply

- clocks                : List of phandle and clock specifier pairs
- clock-names           : List of clock input name strings sorted in the same
                          order as the clocks property.
			  "ref_clk" indicates reference clock frequency.
			  UFS host supplies reference clock to UFS device and UFS device
			  specification allows host to provide one of the 4 frequencies (19.2 MHz,
			  26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
			  parsed and used to update the reference clock setting in device.
			  Defaults to 26 MHz(as per specification) if not specified by host.
- freq-table-hz		: Array of <min max> operating frequencies stored in the same
                          order as the clocks property. If this property is not
			  defined or a value in the array is "0" then it is assumed
			  that the frequency is set by the parent clock or a
			  fixed rate clock source.
-lanes-per-direction	: number of lanes available per direction - either 1 or 2.
			  Note that it is assume same number of lanes is used both
			  directions at once. If not specified, default is 2 lanes per direction.
- #reset-cells		: Must be <1> for Qualcomm UFS controllers that expose
			  PHY reset from the UFS controller.
- resets            : reset node register
- reset-names       : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
- reset-gpios       : A phandle and gpio specifier denoting the GPIO connected
		      to the RESET pin of the UFS memory device.

Note: If above properties are not defined it can be assumed that the supply
regulators or clocks are always on.

Example:
	ufshc@fc598000 {
		compatible = "jedec,ufs-1.1";
		reg = <0xfc598000 0x800>;
		interrupts = <0 28 0>;

		vdd-hba-supply = <&xxx_reg0>;
		vcc-supply = <&xxx_reg1>;
		vcc-supply-1p8;
		vccq-supply = <&xxx_reg2>;
		vccq2-supply = <&xxx_reg3>;
		vcc-max-microamp = 500000;
		vccq-max-microamp = 200000;
		vccq2-max-microamp = 200000;

		clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
		clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
		resets = <&reset 0 1>;
		reset-names = "rst";
		phys = <&ufsphy1>;
		phy-names = "ufsphy";
		#reset-cells = <1>;
	};