Commit 4629adaf authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Pratyush Yadav
Browse files

mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() 



Introduce template operation to remove code duplication.
Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en()
and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to
keep everything alltogether: too many "if (enable)" throughout the code,
which made the code difficult to follow. Add dev_dbg messages in case
spi_nor_read_id() fails.

Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
Reviewed-by: default avatarPratyush Yadav <p.yadav@ti.com>
Reviewed-by: default avatarMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220420103427.47867-8-tudor.ambarus@microchip.com
parent a604ab33

drivers/mtd/spi-nor/micron-st.c

+60 −51
Original line number Diff line number Diff line
@@ -28,75 +28,78 @@ 
#define FSR_P_ERR		BIT(4)	/* Program operation status */

#define FSR_PT_ERR		BIT(1)	/* Protection error bit */



static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)

/* Micron ST SPI NOR flash operations. */

#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf)		\

	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0),		\

		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\

		   SPI_MEM_OP_NO_DUMMY,					\

		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))



static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)

{

	struct spi_mem_op op;

	u8 *buf = nor->bouncebuf;

	int ret;



	if (enable) {

	/* Use 20 dummy cycles for memory array reads. */

		ret = spi_nor_write_enable(nor);

		if (ret)

			return ret;



	*buf = 20;

	op = (struct spi_mem_op)

			SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),

				   SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1),

				   SPI_MEM_OP_NO_DUMMY,

				   SPI_MEM_OP_DATA_OUT(1, buf, 1));



		ret = spi_mem_exec_op(nor->spimem, &op);

		MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)

		return ret;



	ret = spi_nor_wait_till_ready(nor);

	if (ret)

		return ret;

	}



	ret = spi_nor_write_enable(nor);

	buf[0] = SPINOR_MT_OCT_DTR;

	op = (struct spi_mem_op)

		MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)

		return ret;



	if (enable) {

		buf[0] = SPINOR_MT_OCT_DTR;

	} else {

	/* Read flash ID to make sure the switch was successful. */

	ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);

	if (ret) {

		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);

		return ret;

	}



	if (memcmp(buf, nor->info->id, nor->info->id_len))

		return -EINVAL;



	return 0;

}



static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor)

{

	struct spi_mem_op op;

	u8 *buf = nor->bouncebuf;

	int ret;



	/*

		 * The register is 1-byte wide, but 1-byte transactions are not

		 * allowed in 8D-8D-8D mode. The next register is the dummy

		 * cycle configuration register. Since the transaction needs to

		 * be at least 2 bytes wide, set the next register to its

		 * default value. This also makes sense because the value was

		 * changed when enabling 8D-8D-8D mode, it should be reset when

		 * disabling.

	 * The register is 1-byte wide, but 1-byte transactions are not allowed

	 * in 8D-8D-8D mode. The next register is the dummy cycle configuration

	 * register. Since the transaction needs to be at least 2 bytes wide,

	 * set the next register to its default value. This also makes sense

	 * because the value was changed when enabling 8D-8D-8D mode, it should

	 * be reset when disabling.

	 */

	buf[0] = SPINOR_MT_EXSPI;

	buf[1] = SPINOR_REG_MT_CFR1V_DEF;

	}



	op = (struct spi_mem_op)

		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),

			   SPI_MEM_OP_ADDR(enable ? 3 : 4,

					   SPINOR_REG_MT_CFR0V, 1),

			   SPI_MEM_OP_NO_DUMMY,

			   SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));



	if (!enable)

		spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);



	ret = spi_mem_exec_op(nor->spimem, &op);

		MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);

	if (ret)

		return ret;



	/* Read flash ID to make sure the switch was successful. */

	if (enable)

		ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);

	else

	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);

	if (ret)

	if (ret) {

		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);

		return ret;

	}



	if (memcmp(buf, nor->info->id, nor->info->id_len))

		return -EINVAL;
@@ -104,6 +107,12 @@ static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 
	return 0;

}



static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)

{

	return enable ? micron_st_nor_octal_dtr_en(nor) :

			micron_st_nor_octal_dtr_dis(nor);

}



static void mt35xu512aba_default_init(struct spi_nor *nor)

{

	nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable;