Commit 45b2e5ad authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-for-v5.19-2022-06-04' of... 

Merge tag 'perf-tools-for-v5.19-2022-06-04' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull more perf tools updates from Arnaldo Carvalho de Melo:

 - Synthesize task events for pre-existing threads when using 'perf lock
   --threads', as we need to show task names.

 - Fix unwinding with ld.lld (>= version 10.0) linked objects, where
  .eh_frame_hdr and .text are in different PT_LOAD program headers,
   which makes perf record --call-graph dwarf fail with such obkects.

 - Check if 'perf record' hangs in the ARM SPE (Statistical Profiling
   Extensions) 'perf test' entry when recording a workload with forks.

 - Trace physical address for Arm SPE events, needed for 'perf c2c' to
   locate the memory node for samples.

 - Fix sorting in percent_rmt_hitm_cmp() in 'perf c2c'.

 - Further support for Intel hybrid systems in the evlist and 'perf
   record' code.

 - Update IBM s/390 vendor event JSON tables.

 - Add metrics (JSON) for Intel Sapphirerapids.

 - Update metrics for Intel Alderlake.

 - Correct typo of sysf 'event_source' directory in the documentation.

* tag 'perf-tools-for-v5.19-2022-06-04' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux:
  perf vendor events intel: Update metrics for Alderlake
  perf vendor events intel: Add metrics for Sapphirerapids
  perf c2c: Fix sorting in percent_rmt_hitm_cmp()
  perf mem: Trace physical address for Arm SPE events
  perf list: Update event description for IBM zEC12/zBC12 to latest level
  perf list: Update event description for IBM z196/z114 to latest level
  perf list: Update event description for IBM z15 to latest level
  perf list: Update event description for IBM z14 to latest level
  perf list: Update event description for IBM z13 to latest level
  perf list: Update event description for IBM z10 to latest level
  perf list: Add IBM z16 event description for s390
  perf record: Support sample-read topdown metric group for hybrid platforms
  perf lock: Change to synthesize task events
  perf unwind: Fix segbase for ld.lld linked objects
  perf test arm-spe: Check if perf-record hangs when recording workload with forks
  perf docs: Correct typo of event_sources
  perf evlist: Extend arch_evsel__must_be_in_group to support hybrid systems
parents 032dcf09 1bcca2b1

tools/perf/Documentation/perf-record.txt

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ OPTIONS 
        - a raw PMU event in the form of rN where N is a hexadecimal value

          that represents the raw register encoding with the layout of the

          event control registers as described by entries in

          /sys/bus/event_sources/devices/cpu/format/*.

          /sys/bus/event_source/devices/cpu/format/*.



        - a symbolic or raw PMU event followed by an optional colon

	  and a list of event modifiers, e.g., cpu-cycles:p.  See the

tools/perf/Documentation/perf-stat.txt

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ report:: 
	- a raw PMU event in the form of rN where N is a hexadecimal value

	  that represents the raw register encoding with the layout of the

	  event control registers as described by entries in

	  /sys/bus/event_sources/devices/cpu/format/*.

	  /sys/bus/event_source/devices/cpu/format/*.



        - a symbolic or raw PMU event followed by an optional colon

	  and a list of event modifiers, e.g., cpu-cycles:p.  See the

tools/perf/Documentation/perf-top.txt

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ Default is to monitor all CPUS. 
	(use 'perf list' to list all events) or a raw PMU event in the form

	of rN where N is a hexadecimal value that represents the raw register

	encoding with the layout of the event control registers as described

	by entries in /sys/bus/event_sources/devices/cpu/format/*.

	by entries in /sys/bus/event_source/devices/cpu/format/*.



-E <entries>::

--entries=<entries>::

tools/perf/arch/arm64/util/mem-events.c

+3 −3
Original line number Diff line number Diff line
@@ -5,9 +5,9 @@ 
#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s }



static struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = {

	E("spe-load",	"arm_spe_0/ts_enable=1,load_filter=1,store_filter=0,min_latency=%u/",	"arm_spe_0"),

	E("spe-store",	"arm_spe_0/ts_enable=1,load_filter=0,store_filter=1/",			"arm_spe_0"),

	E("spe-ldst",	"arm_spe_0/ts_enable=1,load_filter=1,store_filter=1,min_latency=%u/",	"arm_spe_0"),

	E("spe-load",	"arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/",	"arm_spe_0"),

	E("spe-store",	"arm_spe_0/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/",			"arm_spe_0"),

	E("spe-ldst",	"arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/",	"arm_spe_0"),

};



static char mem_ev_name[100];

tools/perf/arch/x86/util/evsel.c

+3 −2
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include "util/env.h"

#include "util/pmu.h"

#include "linux/string.h"

#include "evsel.h"



void arch_evsel__set_sample_weight(struct evsel *evsel)

{
@@ -32,7 +33,7 @@ void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr) 
}



/* Check whether the evsel's PMU supports the perf metrics */

static bool evsel__sys_has_perf_metrics(const struct evsel *evsel)

bool evsel__sys_has_perf_metrics(const struct evsel *evsel)

{

	const char *pmu_name = evsel->pmu_name ? evsel->pmu_name : "cpu";
@@ -57,6 +58,6 @@ bool arch_evsel__must_be_in_group(const struct evsel *evsel) 
		return false;



	return evsel->name &&

		(!strcasecmp(evsel->name, "slots") ||

		(strcasestr(evsel->name, "slots") ||

		 strcasestr(evsel->name, "topdown"));

}