Commit 45a3681a authored by Fuad Tabba's avatar Fuad Tabba Committed by Oliver Upton
Browse files

KVM: arm64: Use the appropriate feature trap register for SVE at EL2 setup 



Use the architectural feature trap/control register that
corresponds to the current KVM mode, i.e., CPTR_EL2 or CPACR_EL1,
when setting up SVE feature traps.

Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230724123829.2929609-4-tabba@google.com


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent ce922326

arch/arm64/include/asm/el2_setup.h

+9 −6
Original line number Diff line number Diff line
@@ -146,11 +146,12 @@ 
.macro __init_el2_cptr

	__check_hvhe .LnVHE_\@, x1

	mov	x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)

	b	.Lset_cptr_\@

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@

.LnVHE_\@:

	mov	x0, #0x33ff

.Lset_cptr_\@:

	msr	cptr_el2, x0			// Disable copro. traps to EL2

.Lskip_set_cptr_\@:

.endm



/* Disable any fine grained traps */
@@ -271,17 +272,19 @@ 
	check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2



.Linit_sve_\@:	/* SVE register access */

	mrs	x0, cptr_el2			// Disable SVE traps

	__check_hvhe .Lcptr_nvhe_\@, x1



	// VHE case

	// (h)VHE case

	mrs	x0, cpacr_el1			// Disable SVE traps

	orr	x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)

	b	.Lset_cptr_\@

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@



.Lcptr_nvhe_\@: // nVHE case

	mrs	x0, cptr_el2			// Disable SVE traps

	bic	x0, x0, #CPTR_EL2_TZ

.Lset_cptr_\@:

	msr	cptr_el2, x0

.Lskip_set_cptr_\@:

	isb

	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector

	msr_s	SYS_ZCR_EL2, x1			// length for EL1.