Commit 4591c760 authored by Biju Das's avatar Biju Das Committed by Marc Kleine-Budde
Browse files

dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} support 

Add CAN binding documentation for Renesas RZ/N1 SoC.

The SJA1000 CAN controller on RZ/N1 SoC has some differences compared
to others like it has no clock divider register (CDR) support and it has
no HW loopback (HW doesn't see tx messages on rx), so introduced a new
compatible 'renesas,rzn1-sja1000' to handle these differences.

Link: https://lore.kernel.org/all/20220710115248.190280-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent f6b8061d

Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml

+35 −4
Original line number Diff line number Diff line
@@ -11,9 +11,15 @@ maintainers: 


properties:

  compatible:

    enum:

    oneOf:

      - enum:

          - nxp,sja1000

          - technologic,sja1000

      - items:

          - enum:

              - renesas,r9a06g032-sja1000 # RZ/N1D

              - renesas,r9a06g033-sja1000 # RZ/N1S

          - const: renesas,rzn1-sja1000 # RZ/N1



  reg:

    maxItems: 1
@@ -21,6 +27,9 @@ properties: 
  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  reg-io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: I/O register width (in bytes) implemented by this device
@@ -82,10 +91,20 @@ allOf: 
      properties:

        compatible:

          contains:

            const: technologic,sja1000

            enum:

              - technologic,sja1000

              - renesas,rzn1-sja1000

    then:

      required:

        - reg-io-width

  - if:

      properties:

        compatible:

          contains:

            const: renesas,rzn1-sja1000

    then:

      required:

        - clocks



unevaluatedProperties: false
@@ -99,3 +118,15 @@ examples: 
        nxp,tx-output-config = <0x06>;

        nxp,external-clock-frequency = <24000000>;

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/r9a06g032-sysctrl.h>



    can@52104000 {

        compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";

        reg = <0x52104000 0x800>;

        reg-io-width = <4>;

        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&sysctrl R9A06G032_HCLK_CAN0>;

    };