Commit 45826415 authored by Stefan Riedmueller's avatar Stefan Riedmueller Committed by Shawn Guo
Browse files

ARM: dts: imx6ul: segin: Reduce eth drive strength 



Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.

Signed-off-by: default avatarStefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e37816bf

arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -93,16 +93,16 @@ 
&iomuxc {

	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0

			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0

			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x10010

			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x10010

			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0

			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0

			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0

			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0

			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0

			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0

			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0

			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031

			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b010

			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b010

			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b010

			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b010

			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x17059

		>;

	};

arch/arm/boot/dts/imx6ul-phytec-segin.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -230,10 +230,10 @@ 
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0

			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0

			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0

			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0

			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0

			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0

			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031

			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010

			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010

			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010

			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010

		>;

	};