Commit 4567084c authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/gmbus: add wrapper for gmbus mmio base 



Don't repeat the same thing so much.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/db360d824d47601d5ca843afa6f5d6ee17d0e514.1661855191.git.jani.nikula@intel.com
parent 3047d706

drivers/gpu/drm/i915/display/intel_gmbus_regs.h

+9 −8
Original line number Diff line number Diff line
@@ -8,8 +8,9 @@ 


#include "i915_reg_defs.h"



#define GPIO(gpio)		_MMIO(dev_priv->display.gmbus.mmio_base + 0x5010 + \

				      4 * (gpio))

#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)



#define GPIO(gpio)		_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5010 + 4 * (gpio))

#define   GPIO_CLOCK_DIR_MASK		(1 << 0)

#define   GPIO_CLOCK_DIR_IN		(0 << 1)

#define   GPIO_CLOCK_DIR_OUT		(1 << 1)
@@ -26,7 +27,7 @@ 
#define   GPIO_DATA_PULLUP_DISABLE	(1 << 13)



/* clock/port select */

#define GMBUS0			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5100)

#define GMBUS0			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5100)

#define   GMBUS_AKSV_SELECT		(1 << 11)

#define   GMBUS_RATE_100KHZ		(0 << 8)

#define   GMBUS_RATE_50KHZ		(1 << 8)
@@ -36,7 +37,7 @@ 
#define   GMBUS_BYTE_CNT_OVERRIDE	(1 << 6)



/* command/status */

#define GMBUS1			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5104)

#define GMBUS1			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5104)

#define   GMBUS_SW_CLR_INT		(1 << 31)

#define   GMBUS_SW_RDY			(1 << 30)

#define   GMBUS_ENT			(1 << 29) /* enable timeout */
@@ -53,7 +54,7 @@ 
#define   GMBUS_SLAVE_WRITE		(0 << 0)



/* status */

#define GMBUS2			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5108)

#define GMBUS2			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5108)

#define   GMBUS_INUSE			(1 << 15)

#define   GMBUS_HW_WAIT_PHASE		(1 << 14)

#define   GMBUS_STALL_TIMEOUT		(1 << 13)
@@ -63,10 +64,10 @@ 
#define   GMBUS_ACTIVE			(1 << 9)



/* data buffer bytes 3-0 */

#define GMBUS3			_MMIO(dev_priv->display.gmbus.mmio_base + 0x510c)

#define GMBUS3			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x510c)



/* interrupt mask (Pineview+) */

#define GMBUS4			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5110)

#define GMBUS4			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5110)

#define   GMBUS_SLAVE_TIMEOUT_EN	(1 << 4)

#define   GMBUS_NAK_EN			(1 << 3)

#define   GMBUS_IDLE_EN			(1 << 2)
@@ -74,7 +75,7 @@ 
#define   GMBUS_HW_RDY_EN		(1 << 0)



/* byte index */

#define GMBUS5			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5120)

#define GMBUS5			_MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5120)

#define   GMBUS_2BYTE_INDEX_EN		(1 << 31)



#endif /* __INTEL_GMBUS_REGS_H__ */