Commit 4566e2dd authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-x86' 

* pm-x86:
  x86: tsc: Rework time_cpufreq_notifier()
  admin-guide: pm: intel_epb: Add SPDX license tag and copyright notice
  PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfs interface
  PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handling
parents 5a28654c c208ac8f

Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -518,3 +518,21 @@ Description: Control Symetric Multi Threading (SMT) 


			 If control status is "forceoff" or "notsupported" writes

			 are rejected.



What:		/sys/devices/system/cpu/cpu#/power/energy_perf_bias

Date:		March 2019

Contact:	linux-pm@vger.kernel.org

Description:	Intel Energy and Performance Bias Hint (EPB)



		EPB for the given CPU in a sliding scale 0 - 15, where a value

		of 0 corresponds to a hint preference for highest performance

		and a value of 15 corresponds to the maximum energy savings.



		In order to change the EPB value for the CPU, write either

		a number in the 0 - 15 sliding scale above, or one of the

		strings: "performance", "balance-performance", "normal",

		"balance-power", "power" (that represent values reflected by

		their meaning), to this attribute.



		This attribute is present for all online CPUs supporting the

		Intel EPB feature.

Documentation/admin-guide/pm/intel_epb.rst

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.. SPDX-License-Identifier: GPL-2.0

.. include:: <isonum.txt>



======================================

Intel Performance and Energy Bias Hint

======================================



:Copyright: |copy| 2019 Intel Corporation



:Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com>





.. kernel-doc:: arch/x86/kernel/cpu/intel_epb.c

   :doc: overview



Intel Performance and Energy Bias Attribute in ``sysfs``

========================================================



The Intel Performance and Energy Bias Hint (EPB) value for a given (logical) CPU

can be checked or updated through a ``sysfs`` attribute (file) under

:file:`/sys/devices/system/cpu/cpu<N>/power/`, where the CPU number ``<N>``

is allocated at the system initialization time:



``energy_perf_bias``

	Shows the current EPB value for the CPU in a sliding scale 0 - 15, where

	a value of 0 corresponds to a hint preference for highest performance

	and a value of 15 corresponds to the maximum energy savings.



	In order to update the EPB value for the CPU, this attribute can be

	written to, either with a number in the 0 - 15 sliding scale above, or

	with one of the strings: "performance", "balance-performance", "normal",

	"balance-power", "power" that represent values reflected by their

	meaning.



	This attribute is present for all online CPUs supporting the EPB

	feature.



Note that while the EPB interface to the processor is defined at the logical CPU

level, the physical register backing it may be shared by multiple CPUs (for

example, SMT siblings or cores in one package).  For this reason, updating the

EPB value for one CPU may cause the EPB values for other CPUs to change.

Documentation/admin-guide/pm/working-state.rst

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@@ -8,3 +8,4 @@ Working-State Power Management 
   cpuidle

   cpufreq

   intel_pstate

   intel_epb

arch/x86/kernel/cpu/Makefile

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@@ -28,7 +28,7 @@ obj-y += cpuid-deps.o 
obj-$(CONFIG_PROC_FS)	+= proc.o

obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o



obj-$(CONFIG_CPU_SUP_INTEL)		+= intel.o intel_pconfig.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= intel.o intel_pconfig.o intel_epb.o

obj-$(CONFIG_CPU_SUP_AMD)		+= amd.o

obj-$(CONFIG_CPU_SUP_HYGON)		+= hygon.o

obj-$(CONFIG_CPU_SUP_CYRIX_32)		+= cyrix.o

arch/x86/kernel/cpu/common.c

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@@ -1864,23 +1864,6 @@ void cpu_init(void) 
}

#endif



static void bsp_resume(void)

{

	if (this_cpu->c_bsp_resume)

		this_cpu->c_bsp_resume(&boot_cpu_data);

}



static struct syscore_ops cpu_syscore_ops = {

	.resume		= bsp_resume,

};



static int __init init_cpu_syscore(void)

{

	register_syscore_ops(&cpu_syscore_ops);

	return 0;

}

core_initcall(init_cpu_syscore);



/*

 * The microcode loader calls this upon late microcode load to recheck features,

 * only when microcode has been updated. Caller holds microcode_mutex and CPU