Loading arch/arc/Kconfig +0 −4 Original line number Diff line number Diff line Loading @@ -117,10 +117,6 @@ config CPU_BIG_ENDIAN help Build kernel for Big Endian Mode of ARC CPU # If a platform can't work with 0x8000_0000 based dma_addr_t config ARC_PLAT_NEEDS_CPU_TO_DMA bool config SMP bool "Symmetric Multi-Processing (Incomplete)" default n Loading arch/arc/include/asm/dma-mapping.h +5 −26 Original line number Diff line number Diff line Loading @@ -14,23 +14,6 @@ #include <asm-generic/dma-coherent.h> #include <asm/cacheflush.h> #ifndef CONFIG_ARC_PLAT_NEEDS_CPU_TO_DMA /* * dma_map_* API take cpu addresses, which is kernel logical address in the * untranslated address space (0x8000_0000) based. The dma address (bus addr) * ideally needs to be 0x0000_0000 based hence these glue routines. * However given that intermediate bus bridges can ignore the high bit, we can * do with these routines being no-ops. * If a platform/device comes up which sriclty requires 0 based bus addr * (e.g. AHB-PCI bridge on Angel4 board), then it can provide it's own versions */ #define plat_dma_addr_to_kernel(dev, addr) ((unsigned long)(addr)) #define plat_kernel_addr_to_dma(dev, ptr) ((dma_addr_t)(ptr)) #else #include <plat/dma_addr.h> #endif void *dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp); Loading Loading @@ -94,7 +77,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { _dma_cache_sync((unsigned long)cpu_addr, size, dir); return plat_kernel_addr_to_dma(dev, cpu_addr); return (dma_addr_t)cpu_addr; } static inline void Loading Loading @@ -147,16 +130,14 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle), size, DMA_FROM_DEVICE); _dma_cache_sync(dma_handle, size, DMA_FROM_DEVICE); } static inline void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle), size, DMA_TO_DEVICE); _dma_cache_sync(dma_handle, size, DMA_TO_DEVICE); } static inline void Loading @@ -164,8 +145,7 @@ dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle) + offset, size, DMA_FROM_DEVICE); _dma_cache_sync(dma_handle + offset, size, DMA_FROM_DEVICE); } static inline void Loading @@ -173,8 +153,7 @@ dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle) + offset, size, DMA_TO_DEVICE); _dma_cache_sync(dma_handle + offset, size, DMA_TO_DEVICE); } static inline void Loading arch/arc/mm/dma.c +4 −8 Original line number Diff line number Diff line Loading @@ -14,8 +14,6 @@ * Cache bit off in the TLB entry. * * The default DMA address == Phy address which is 0x8000_0000 based. * A platform/device can make it zero based, by over-riding * plat_{dma,kernel}_addr_to_{kernel,dma} */ #include <linux/dma-mapping.h> Loading @@ -37,7 +35,7 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size, return NULL; /* This is bus address, platform dependent */ *dma_handle = plat_kernel_addr_to_dma(dev, paddr); *dma_handle = (dma_addr_t)paddr; return paddr; } Loading @@ -46,8 +44,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle), size); free_pages_exact((void *)dma_handle, size); } EXPORT_SYMBOL(dma_free_noncoherent); Loading @@ -67,7 +64,7 @@ void *dma_alloc_coherent(struct device *dev, size_t size, memset(kvaddr, 0, size); /* This is bus address, platform dependent */ *dma_handle = plat_kernel_addr_to_dma(dev, paddr); *dma_handle = (dma_addr_t)paddr; return kvaddr; } Loading @@ -78,8 +75,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *kvaddr, { iounmap((void __force __iomem *)kvaddr); free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle), size); free_pages_exact((void *)dma_handle, size); } EXPORT_SYMBOL(dma_free_coherent); Loading Loading
arch/arc/Kconfig +0 −4 Original line number Diff line number Diff line Loading @@ -117,10 +117,6 @@ config CPU_BIG_ENDIAN help Build kernel for Big Endian Mode of ARC CPU # If a platform can't work with 0x8000_0000 based dma_addr_t config ARC_PLAT_NEEDS_CPU_TO_DMA bool config SMP bool "Symmetric Multi-Processing (Incomplete)" default n Loading
arch/arc/include/asm/dma-mapping.h +5 −26 Original line number Diff line number Diff line Loading @@ -14,23 +14,6 @@ #include <asm-generic/dma-coherent.h> #include <asm/cacheflush.h> #ifndef CONFIG_ARC_PLAT_NEEDS_CPU_TO_DMA /* * dma_map_* API take cpu addresses, which is kernel logical address in the * untranslated address space (0x8000_0000) based. The dma address (bus addr) * ideally needs to be 0x0000_0000 based hence these glue routines. * However given that intermediate bus bridges can ignore the high bit, we can * do with these routines being no-ops. * If a platform/device comes up which sriclty requires 0 based bus addr * (e.g. AHB-PCI bridge on Angel4 board), then it can provide it's own versions */ #define plat_dma_addr_to_kernel(dev, addr) ((unsigned long)(addr)) #define plat_kernel_addr_to_dma(dev, ptr) ((dma_addr_t)(ptr)) #else #include <plat/dma_addr.h> #endif void *dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp); Loading Loading @@ -94,7 +77,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { _dma_cache_sync((unsigned long)cpu_addr, size, dir); return plat_kernel_addr_to_dma(dev, cpu_addr); return (dma_addr_t)cpu_addr; } static inline void Loading Loading @@ -147,16 +130,14 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle), size, DMA_FROM_DEVICE); _dma_cache_sync(dma_handle, size, DMA_FROM_DEVICE); } static inline void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle), size, DMA_TO_DEVICE); _dma_cache_sync(dma_handle, size, DMA_TO_DEVICE); } static inline void Loading @@ -164,8 +145,7 @@ dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle) + offset, size, DMA_FROM_DEVICE); _dma_cache_sync(dma_handle + offset, size, DMA_FROM_DEVICE); } static inline void Loading @@ -173,8 +153,7 @@ dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { _dma_cache_sync(plat_dma_addr_to_kernel(dev, dma_handle) + offset, size, DMA_TO_DEVICE); _dma_cache_sync(dma_handle + offset, size, DMA_TO_DEVICE); } static inline void Loading
arch/arc/mm/dma.c +4 −8 Original line number Diff line number Diff line Loading @@ -14,8 +14,6 @@ * Cache bit off in the TLB entry. * * The default DMA address == Phy address which is 0x8000_0000 based. * A platform/device can make it zero based, by over-riding * plat_{dma,kernel}_addr_to_{kernel,dma} */ #include <linux/dma-mapping.h> Loading @@ -37,7 +35,7 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size, return NULL; /* This is bus address, platform dependent */ *dma_handle = plat_kernel_addr_to_dma(dev, paddr); *dma_handle = (dma_addr_t)paddr; return paddr; } Loading @@ -46,8 +44,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle), size); free_pages_exact((void *)dma_handle, size); } EXPORT_SYMBOL(dma_free_noncoherent); Loading @@ -67,7 +64,7 @@ void *dma_alloc_coherent(struct device *dev, size_t size, memset(kvaddr, 0, size); /* This is bus address, platform dependent */ *dma_handle = plat_kernel_addr_to_dma(dev, paddr); *dma_handle = (dma_addr_t)paddr; return kvaddr; } Loading @@ -78,8 +75,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *kvaddr, { iounmap((void __force __iomem *)kvaddr); free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle), size); free_pages_exact((void *)dma_handle, size); } EXPORT_SYMBOL(dma_free_coherent); Loading