Commit 4547700a authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
Browse files

KVM: x86: Consolidate APIC base RESET initialization code 



Consolidate the APIC base RESET logic, which is currently spread out
across both x86 and vendor code.  For an in-kernel APIC, the vendor code
is redundant.  But for a userspace APIC, KVM relies on the vendor code
to initialize vcpu->arch.apic_base.  Hoist the vcpu->arch.apic_base
initialization above the !apic check so that it applies to both flavors
of APIC emulation, and delete the vendor code.

Reviewed-by: default avatarReiji Watanabe <reijiw@google.com>
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20210713163324.627647-19-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 42122123

arch/x86/kvm/lapic.c

+7 −5
Original line number Diff line number Diff line
@@ -2323,6 +2323,13 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) 
	struct kvm_lapic *apic = vcpu->arch.apic;

	int i;



	if (!init_event) {

		vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |

				       MSR_IA32_APICBASE_ENABLE;

		if (kvm_vcpu_is_reset_bsp(vcpu))

			vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;

	}



	if (!apic)

		return;
@@ -2330,11 +2337,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) 
	hrtimer_cancel(&apic->lapic_timer.timer);



	if (!init_event) {

		vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |

				       MSR_IA32_APICBASE_ENABLE;

		if (kvm_vcpu_is_reset_bsp(vcpu))

			vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;



		apic->base_address = APIC_DEFAULT_PHYS_BASE;



		kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);

arch/x86/kvm/svm/svm.c

+0 −6
Original line number Diff line number Diff line
@@ -1336,12 +1336,6 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 
	svm->spec_ctrl = 0;

	svm->virt_spec_ctrl = 0;



	if (!init_event) {

		vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |

				       MSR_IA32_APICBASE_ENABLE;

		if (kvm_vcpu_is_reset_bsp(vcpu))

			vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;

	}

	init_vmcb(vcpu);



	/*

arch/x86/kvm/vmx/vmx.c

+0 −7
Original line number Diff line number Diff line
@@ -4407,13 +4407,6 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 
	vmx->hv_deadline_tsc = -1;

	kvm_set_cr8(vcpu, 0);



	if (!init_event) {

		vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |

				       MSR_IA32_APICBASE_ENABLE;

		if (kvm_vcpu_is_reset_bsp(vcpu))

			vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;

	}



	vmx_segment_cache_clear(vmx);



	seg_setup(VCPU_SREG_CS);